Quantum Computing Modalities: Superconducting Qubits

(For other quantum computing modalities and architectures, see Taxonomy of Quantum Computing: Modalities & Architectures)

What It Is

Superconducting qubits are quantum bits built from tiny electrical circuits cooled to temperatures colder than deep space. At roughly 10–20 millikelvin (about 0.01 degrees above absolute zero), certain metals like aluminum and niobium become superconducting, carrying current with zero resistance. When a Josephson junction (a thin insulating barrier sandwiched between two superconductors) is wired into an LC oscillator circuit, the result is an artificial atom whose quantized energy levels serve as the |0⟩ and |1⟩ states of a qubit.

The Josephson junction is what makes the whole thing work. Without it, an LC circuit is just a harmonic oscillator with evenly spaced energy levels and no way to isolate two of them for computation. The junction introduces anharmonicity, an uneven spacing that allows microwave pulses at one specific frequency (typically 4–8 GHz) to address the |0⟩ → |1⟩ transition without accidentally exciting higher states. That selectivity is the foundation of all gate operations on superconducting qubits.

This modality dominates quantum computing today. IBM, Google, Rigetti, IQM, QuantWare, OQC, and dozens of other organizations worldwide build processors on superconducting qubits. Google’s 53-qubit Sycamore chip produced the first quantum supremacy demonstration in 2019. IBM crossed 1,000 physical qubits with Condor in 2023. Google’s Willow demonstrated below-threshold error correction in December 2024. And QuantWare, the largest commercial QPU supplier by volume, raised $178 million in May 2026 to fund a 10,000-qubit processor architecture.

From a CRQC standpoint, superconducting qubits are the modality most likely to underpin the first cryptographically relevant quantum computer, alongside trapped ions. Their combination of fast gate speeds, mature fabrication processes, and rapid error correction progress makes them the platform to watch for anyone in the business of protecting data.

How It Works

The Josephson Junction

Every superconducting qubit centers on a Josephson junction. Brian Josephson predicted in 1962 that Cooper pairs (paired electrons in a superconductor) could tunnel through a thin insulating barrier without resistance. That tunneling gives the junction a nonlinear inductance. Wire it into an LC circuit, and the energy spectrum becomes anharmonic: the gap between the first and second energy levels differs from the gap between the second and third. The bottom two levels become a usable qubit.

The junction’s critical current, the barrier thickness, and the shunt capacitance together set the qubit’s operating frequency and its sensitivity to various noise sources. Getting these parameters right is a fabrication challenge that has driven 25 years of iterative improvement.

Qubit Types

Several superconducting qubit designs have been developed, each balancing coherence, controllability, and noise sensitivity differently:

Transmon (Koch et al., 2007). The workhorse of the field. A charge qubit with a large shunt capacitor that strongly suppresses sensitivity to charge noise. The tradeoff is reduced anharmonicity (~200–300 MHz), but it’s enough for selective gate operations. Transmons are used in nearly every major superconducting processor: IBM’s Heron and Condor families, Google’s Willow, QuantWare’s product line, IQM’s Radiance, and Rigetti’s Ankaa-3. Variants include the Xmon (planar, X-shaped capacitor, used by Google), the Coaxmon (OQC’s 3D design with components on opposite sides of the substrate), and the gatemon (using a semiconductor nanowire for voltage-tunable Josephson energy).

Fluxonium (Manucharyan et al., 2009). A qubit with a large superinductor (a chain of hundreds of Josephson junctions) that provides much greater anharmonicity than the transmon while maintaining long coherence. In 2021, a University of Maryland group demonstrated fluxonium with T₂* = 1.48 ms (Ramsey coherence), an order of magnitude beyond transmon records at the time. Alibaba’s quantum laboratory reported a fluxonium processor with 99.97% single-qubit and 99.72% two-qubit gate fidelity. Fluxonium is increasingly seen as the transmon’s successor for applications demanding maximum coherence, though scaling it to large arrays remains a more recent engineering effort. Atlantic Quantum is pursuing fluxonium-based processors under DARPA’s QBI program.

Flux qubits. Superconducting loops with one or more junctions, encoding states in clockwise versus counter-clockwise circulating currents. D-Wave uses flux qubits for quantum annealing, scaling to over 5,000 qubits on its Advantage platform. For gate-based computation, flux qubits have largely been overtaken by transmons, though variants like the capacitively shunted flux qubit still appear in research.

Cat qubits. A bosonic encoding where quantum information lives in a superposition of two coherent microwave states (|α⟩ and |−α⟩) inside a superconducting resonator. The encoding provides built-in bit-flip protection while requiring active correction only for phase flips. Alice & Bob demonstrated a cat qubit with a one-hour bit-flip time in September 2025, and AWS’s Ocelot chip validated the cat-qubit approach with a 100× reduction in error correction overhead. I cover cat qubits in depth in a separate modality article.

Coupling and Gates

Single-qubit gates are implemented by applying calibrated microwave pulses at the qubit’s resonant frequency. A typical single-qubit gate (an X or Y rotation) uses a Gaussian or DRAG-shaped envelope lasting 10–50 ns. DRAG (Derivative Removal by Adiabatic Gate) pulses add a derivative component to the in-phase pulse to suppress leakage from the computational subspace into the |2⟩ state, a correction made necessary by the transmon’s relatively small anharmonicity. Calibrating DRAG coefficients, drive amplitudes, and frequency detunings is a per-qubit process that must be repeated regularly as parameters drift.

Two-qubit entangling gates come in several architectures, and the choice has significant implications for system design:

Cross-resonance (CR). Used by IBM. One transmon is driven at the frequency of a coupled, fixed-frequency neighbor. The off-resonant drive produces an effective ZX interaction that, over a calibrated duration, implements a CNOT-equivalent gate. The echoed-CR variant (driving for half the gate time, applying a local π rotation, then driving again) cancels unwanted single-qubit and ZZ terms, improving fidelity. The advantage of cross-resonance is that it works with fixed-frequency transmons (no flux-tunable junctions), simplifying fabrication and eliminating flux noise. The disadvantage is longer gate times (200–500 ns) compared to flux-based approaches.

Tunable couplers. Used by Google, QuantWare, Rigetti, and IQM. A third superconducting element (typically a transmon-like coupler qubit) sits between two computational qubits. Flux-tuning the coupler modulates the effective coupling strength, enabling clean CZ or iSWAP gates in 20–100 ns. When the coupler is parked at its “off” point, residual ZZ coupling between the computational qubits is suppressed below 50 kHz (ideally below 10 kHz). This on/off ratio is critical for scaling: persistent ZZ coupling accumulates phase errors on idling qubits during gates on their neighbors. Tunable couplers require flux lines and are sensitive to flux noise, but they deliver the fastest two-qubit gates with the best fidelity. Google’s Willow CZ gate, QuantWare’s tunable-coupler Contralto-A3, and Rigetti’s iSWAP all use this approach.

Parametric gates. Instead of flux-biasing a coupler to a static operating point, a modulated flux tone at the frequency difference between two qubits activates the coupling resonantly. This allows entangling gates between fixed-frequency qubits without a dedicated tunable coupler, though the gate times are typically longer than direct coupler-mediated approaches.

Readout

Readout uses the dispersive interaction between each qubit and a dedicated readout resonator. When the qubit is in |0⟩, the resonator sits at one frequency; when in |1⟩, the resonator shifts by 2χ (the dispersive shift, typically 1–5 MHz). A microwave probe pulse at the resonator frequency acquires a state-dependent phase and amplitude, which is digitized and classified in the IQ (in-phase/quadrature) plane. The result is two clusters (one for |0⟩, one for |1⟩) whose separation determines readout fidelity.

High-fidelity readout requires near-quantum-limited amplification. At the millikelvin stage, a traveling-wave parametric amplifier (TWPA) provides ~20 dB of gain with noise near the quantum limit. Silent Waves’ Zephyr (launched March 2026) integrates the TWPA and pump coupler into a single package. Above the TWPA, a high-electron-mobility transistor (HEMT) amplifier at 4 K adds another ~40 dB of gain before the signal reaches room-temperature digitizers. Circulators between the qubit and TWPA prevent amplifier back-action from disturbing the qubits.

Modern systems achieve single-shot readout fidelity above 97.5% (QuantWare Gen-D spec) to 99.5% (Google Willow). Purcell filters, integrated into QPU designs like QuantWare’s Contralto-A3, prevent the readout resonator from limiting qubit T₁ through spontaneous emission (the Purcell effect).

The Physical Infrastructure

All of this operates inside a dilution refrigerator, a complex cryogenic system that cools the QPU to 10–20 mK through a mixture of helium-3 and helium-4 isotopes. The signal chain connecting room-temperature electronics to the millikelvin processor is itself a precision engineering challenge: each qubit’s drive line typically passes through 60 dB of attenuation across five temperature stages, with infrared filters, DC blocks, and magnetic shields ensuring that thermal noise from 300 K electronics does not reach the qubits.

I cover the cryogenic infrastructure, wiring, control electronics, and the full bill of materials for building a superconducting quantum computer in my dedicated deep dives on cryogenic infrastructure, building a superconducting system, and facility preparation.

Coherence: Where Things Stand

Coherence time is the clock that ticks down on every quantum computation. Two metrics matter: T₁ (how long the qubit holds its energy before decaying) and T₂ (how long superposition phase relationships survive).

In July 2025, a team at Aalto University in Finland published a transmon qubit with T₁ median of 425 µs and maximum of 666 µs, and an echo dephasing time T₂ reaching 1.06 ms. That’s roughly a 10× improvement over what was typical five years ago. Princeton separately demonstrated a qubit with 1 ms coherence in 2025. On the fluxonium side, T₂* values above 1 ms were demonstrated as early as 2021.

These numbers matter because they determine the maximum circuit depth before noise drowns out the signal. At a 5 GHz operating frequency with 100 µs coherence, you get roughly 10,000 gate operations before the qubit forgets what it was doing. At 500 µs, that budget grows to 50,000, changing the class of algorithms you can run.

Noise Sources and Materials Engineering

The pursuit of longer coherence is fundamentally a materials science and fabrication engineering problem. Each noise mechanism limits coherence through a different physical channel:

Surface dielectric loss. The dominant T₁ limiter in transmon qubits. Native oxide layers (Nb₂O₅ on niobium, Al₂O₃ on aluminum) at the metal-substrate and metal-air interfaces host two-level system (TLS) defects: microscopic atomic configurations that fluctuate between two states, absorbing and re-emitting energy at the qubit’s frequency. A single TLS resonant with the qubit can reduce T₁ by an order of magnitude. The “surface participation ratio” quantifies what fraction of the qubit’s electric field energy resides in these lossy surface layers. Reducing this ratio, through larger qubit geometries, suspended structures, or cleaner interfaces, directly improves T₁.

The most impactful materials improvement of the past five years has been the replacement of niobium capacitor pads with tantalum. A 2021 Princeton result demonstrated that tantalum-on-sapphire transmons achieved T₁ > 300 µs, roughly 3× better than niobium-on-silicon devices of similar geometry. The Aalto record-setting qubit used high-quality superconducting films from VTT Finland on a sapphire substrate. Substrate choice matters: sapphire has lower intrinsic dielectric loss than silicon, but silicon is easier to integrate with CMOS processes. IBM uses silicon substrates for manufacturing scalability; academic groups and some vendors prefer sapphire for peak coherence.

Two-level system (TLS) defects. Beyond surface losses, TLS defects exist in the junction barrier (the thin AlOx layer of the Josephson junction itself), in the substrate bulk, and at substrate-metal interfaces. These defects are stochastic: a qubit may show excellent T₁ on one cooldown and poor T₁ on the next, because TLS defects reconfigure randomly during thermal cycling. This TLS “lottery” is one reason that vendor-specified coherence times are typically stated as averages across multiple cooldowns, not guarantees. QuantWare addresses this with pre-delivery cryogenic characterization of every chip.

Quasiparticle poisoning. Cooper pairs in a superconductor can be broken into unpaired electrons (quasiparticles) by stray infrared photons leaking through the cryogenic signal chain or by cosmic rays impacting the substrate. A single quasiparticle tunneling across the Josephson junction causes a T₁ relaxation event. Infrared (eccosorb) filters at the cold plate and mixing chamber stages block thermal photons. Cosmic-ray mitigation is harder: a cosmic ray impact can generate thousands of quasiparticles across a chip simultaneously, causing correlated errors on multiple qubits. Google’s Willow team has studied this effect extensively. Shielding (lead or concrete), underground operation, and fast quasiparticle trapping are active research areas, but there is currently no complete solution.

Flux noise. For flux-tunable transmons and fluxonium qubits, magnetic flux noise from paramagnetic impurities on electrode surfaces causes dephasing. Operating at a “sweet spot” (where the qubit frequency is first-order insensitive to flux) suppresses this, but second-order sensitivity remains. Fixed-frequency transmons (IBM’s approach) avoid flux noise entirely by eliminating the flux-tuning degree of freedom, at the cost of less flexible two-qubit gate schemes.

Gate Fidelities: The 2026 Scorecard

As of May 2026, the best published gate fidelities on superconducting qubits are:

Metric	Leader	Value	Source
Single-qubit gate	Google Willow	99.97%	Nature, Dec 2024
Two-qubit gate (CZ)	Google Willow	99.67% (best), 99.88% (median entangling)	Nature, Dec 2024
Two-qubit gate (iSWAP)	Rigetti Ankaa-3	99.0% median	Rigetti, Dec 2024
Two-qubit gate (fSim)	Rigetti Ankaa-3	99.5% median	Rigetti, Dec 2024
Two-qubit gate (CZ, fastest)	Oxford/OQC	99.8% in 25 ns	OQC, Mar 2025
Readout	Google Willow	99.5%	Nature, Dec 2024
Fluxonium 2Q	Alibaba	99.72%	arXiv, 2021
IQM target	IQM Halocene	99.7% 2Q (targeting)	IQM, Nov 2025

For context: surface-code quantum error correction demands per-gate physical error rates below roughly 1% (the threshold varies by code, but 0.5–1% is the general target). Google’s Willow, with ~0.3% two-qubit error rates, operates comfortably below threshold. That’s exactly why its below-threshold QEC result was a defining moment for the field.

Key Academic Papers

The literature on superconducting qubits spans three decades. These are the papers that moved the field forward, organized by the capability they unlocked. I’ve weighted recent papers more heavily because the earlier history is well-covered elsewhere.

Foundational (1999–2007)

Nakamura, Pashkin & Tsai (1999). First coherent control of a Cooper-pair box qubit, demonstrating Rabi oscillations with nanosecond coherence. Proved that Josephson circuits could function as two-level quantum systems. Published in Nature.

Koch et al. (2007). Introduced the transmon qubit by adding a large shunt capacitor to suppress charge noise. The design that enabled everything IBM and Google built afterward. Published in Physical Review A.

Wallraff et al. (2004); Blais et al. (2004). Established circuit quantum electrodynamics (cQED): strong coupling between superconducting qubits and microwave cavities. This architecture provides the readout mechanism and inter-qubit coupling bus used in every modern processor. Published in Nature and Physical Review A respectively.

Scaling and Supremacy (2019–2023)

Arute et al. / Google (2019). A 53-qubit Sycamore processor performed random circuit sampling in 200 seconds, a task estimated to take 10,000 years classically. The first quantum supremacy demonstration. Published in Nature. My analysis.

Wu et al. / USTC (2021). Zuchongzhi 66-qubit processor performed a similar sampling task, extending Google’s approach and demonstrating that Chinese teams could match Western hardware capability. The Zuchongzhi line continued through 3.0 (105 qubits, 2025) and 3.2 (below threshold, 2025).

Kim et al. / IBM (2023). Demonstrated that a 127-qubit Eagle processor could produce results on a kicked Ising model that matched exact simulations at small scales and remained reliable at scales beyond classical simulation capacity. Published in Nature. This was IBM’s first claim of quantum utility, though the classical simulation community contested aspects of it.

Error Correction and Coherence Breakthroughs (2024–2026)

Acharya et al. / Google (2024, published Nature 2025). The 105-qubit Willow chip demonstrated below-threshold surface code error suppression. As code distance grew from 3 to 5 to 7, logical error rates dropped exponentially with Λ = 2.14 ± 0.02. Also demonstrated real-time error correction and “beyond breakeven” operation where logical qubit lifetimes exceeded physical qubit lifetimes. The most significant error correction result in the field’s history. My analysis.

Somoroff et al. / Maryland (2021, published PRL 2023). Fluxonium qubit with T₂* = 1.48 ms Ramsey coherence, an order of magnitude beyond prior records for any superconducting qubit. Demonstrated that the fluxonium architecture could achieve coherence previously thought limited to atomic systems.

Tuokkola et al. / Aalto (2025). Transmon qubit with T₁ median of 425 µs (maximum 666 µs) and T₂-echo reaching 1.06 ms, published in Nature Communications. This broke the millisecond barrier for transmon echo coherence. The qubit used high-quality superconducting films from VTT Finland.

Google / Quantum Echoes (October 2025, Nature). First verifiable quantum advantage: Willow mapped a molecule’s features 13,000× faster than classical supercomputers, with reproducible, checkable results. Distinguished from prior “beyond-classical” demonstrations by the verifiability criterion. My analysis.

IBM / Concatenated Gross code (May 2026). Reached the teraquop regime (10¹² error-free operations) using concatenated qLDPC codes. The strongest evidence that high-rate codes can reduce the physical overhead of fault tolerance by an order of magnitude versus surface codes. My analysis.

IBM / Quantum advantage with Heron-Fugaku (May 2026). Demonstrated that a Heron-class processor coupled with Fugaku classical supercomputer could solve certain problems beyond classical reach. The claim requires careful parsing. My analysis.

Resource Estimation Papers (Relevant to Cryptographic Threat)

Gidney (2025). Reduced the estimated resources for factoring RSA-2048 via Shor’s algorithm to ~1,400 logical qubits and ~6.5 billion Toffoli gates, down from the prior Gidney & Ekerå 2021 estimate of 20 million physical qubits. My deep analysis.

Chevignard, Fouque & Schrottenloher (EUROCRYPT 2026). Estimated 1,193 logical qubits for breaking P-256 ECDLP, the first rigorous resource estimate for attacking the specific elliptic curve that secures most of today’s TLS connections. I discuss this paper in detail in my analysis of the 1,000-qubit ceiling and its implications for Google’s ECDLP resource estimates.

Babbush et al. / Google (2026, arXiv:2603.28846). Reduced ECDLP qubit requirements by roughly 10× from prior estimates, using improved windowed arithmetic and optimized circuit compilation.

The Vendor Landscape (May 2026)

The superconducting qubit ecosystem has bifurcated into two models: vertically integrated system builders (who sell or provide access to complete quantum computers) and component suppliers operating under Quantum Open Architecture (QOA) principles, where QPUs, cryostats, control electronics, and software come from different vendors. Both matter. The integrated players set performance benchmarks; the QOA players determine whether anyone outside of IBM, Google, and a handful of national labs can actually build or operate a superconducting quantum computer.

Vertically Integrated System Builders

IBM. The most transparent roadmap in the industry. IBM shipped the 127-qubit Eagle (2021), 433-qubit Osprey (2022), 1,121-qubit Condor (2023), and 156-qubit Heron R2 (2024). In November 2025, IBM unveiled the Nighthawk and Loon processors, with Loon introducing c-couplers for the non-local connectivity required by qLDPC codes. The updated roadmap targets Kookaburra (first fault-tolerant module with logic and memory, 2026), Cockatoo (two linked modules, 2027), and Starling (200 logical qubits running 100 million operations, 2029) at a new quantum data center in Poughkeepsie, NY. The long-term target is Blue Jay: 2,000 logical qubits, 1 billion operations, post-2033. IBM’s shift to qLDPC codes (specifically the Gross code) reduces physical qubit overhead by up to 90% compared to surface codes. In May 2026, IBM published a concatenated Gross code result reaching the teraquop regime. IBM does not sell standalone QPUs.

Google. Focused on quality over qubit count. The 105-qubit Willow chip (December 2024) achieved below-threshold error suppression on a surface code, 99.97% single-qubit fidelity, 99.88% two-qubit entangling fidelity, and 99.5% readout fidelity across its entire array. In October 2025, Google demonstrated verifiable quantum advantage on Willow using the Quantum Echoes algorithm. Google’s stated goal is a useful, error-corrected quantum computer by the end of the decade. Google does not sell hardware externally.

Rigetti. The 84-qubit Ankaa-3 (December 2024) halved error rates to 99.0% median iSWAP and 99.5% median fSim gate fidelity. Rigetti ships the 9-qubit Novera QPU (~$900k, 4–6 week delivery) as a standalone component for integrators. Rigetti’s mid-2025 target was a 36-qubit chiplet-based system, with a 100+ qubit system by end of 2025. Cloud access via Rigetti QCS, Amazon Braket, and Azure Quantum.

IQM (Finland). The most active European vendor for on-premises deployments. The IQM Radiance line ships in 20, 54, and 150-qubit configurations with 99.9% single-qubit fidelity and tunable couplers natively supporting surface-code layouts. Euro-Q-Exa, the first EuroHPC quantum computer in Germany, became operational at LRZ in February 2026 with a 54-qubit Radiance processor, with 150 qubits planned by late 2026. IQM also announced a 300-qubit system for VTT Finland (2027) and the Halocene product line for QEC research, targeting 99.7% two-qubit fidelity. The Constellation architecture uses a hexagonal topology optimized for color codes and qLDPC codes. IQM is going public via a $1.8 billion SPAC deal announced February 2026. IQM sells complete on-premises systems, not standalone QPUs.

OQC (Oxford Quantum Circuits, UK). Built around the patented Coaxmon (a 3D transmon variant with components on opposite substrate faces). Toshiko is a 32-qubit system deployed in commercial data centers. The Genesis system (2026) will introduce OQC’s Dimon dual-rail qubits. In March 2025, OQC’s Oxford research group demonstrated a 25 ns CZ gate at 99.8% fidelity, the fastest high-fidelity two-qubit gate ever measured. OQC’s long-term roadmap targets 50,000 logical qubits on a single 300 mm wafer, though that is very much a roadmap claim. OQC is an NVQLink partner with Riverlane Deltaflow 2 deployed at its CentreSquare facility.

QOA Component Suppliers (QPUs You Can Buy)

QuantWare (Netherlands). The largest commercial QPU supplier by volume, with hardware shipped to over 50 customers across 20 countries. Product line: Soprano-D5 (5 qubits, ~€60k), Contralto-D21 (21 qubits, ~€300k), Contralto-A3 (17 qubits, QEC-optimized with distance-3 surface code layout), and Tenor-D64 (64 qubits, deployed at the University of Naples). Gen-D performance: ~60 µs average coherence, 99.9% vendor-typical single-qubit fidelity, 99.7% two-qubit fidelity, 97.5% readout fidelity. In May 2026, QuantWare raised $178 million in a Series B led by Intel Capital and IQT to fund KiloFab (a dedicated QPU fab in Delft) and the VIO-40K modular architecture targeting 10,000 qubits by 2028. VIO-40K first shipments are scheduled for 2028; these are roadmap items, not delivered products. QuantWare is the QPU behind the Q-PAC deployment in Denver and the Tuna-5 open-architecture system in Delft.

Rigetti Novera. 9 transmon qubits in a 3×3 lattice with tunable couplers. ~$900k for the QPU; complete systems with upgrade packages reported at ~$2.85M. T₁ = 45.9 µs, T₂-echo = 25.5 µs on representative qubits. 4–6 week delivery. Compatible with any cryostat with ≥290 mm MXC plate.

These are the only two sources from which an integrator can currently buy a standalone superconducting QPU and assemble a system with independent cryogenics, control electronics, and software. For details on how such a system gets built, see my deep dive on building a superconducting quantum computer and the broader series on building a quantum computer from off-the-shelf components.

Chinese Ecosystem

China’s superconducting program is extensive and increasingly self-sufficient. The main players:

USTC (University of Science and Technology of China, Hefei). Source of the Zuchongzhi processor line. Zuchongzhi 3.0 (105 qubits, 2025) achieved random circuit sampling beyond classical simulation capacity. Zuchongzhi 3.2 (late 2025) crossed the error correction threshold using a different approach from Google’s surface code, demonstrating that Chinese hardware is operating at the same quality frontier as Western leaders. USTC also demonstrated Jiuzhang photonic quantum advantage and the Xiaohong 504-qubit chip.

Origin Quantum (Hefei). The most complete Chinese QOA analogue, building chips, cryostats, control electronics, and software in-house. The Wukong third-generation 72-qubit QPU has processed over 339,000 jobs. Published T₁ of 15.22 µs and T₂ of 2.23 µs represent a significant gap versus Western leaders (QuantWare’s Gen-D spec is 60 µs average coherence). Origin released the first publicly downloadable quantum operating system (Origin Pilot V4.0) in February 2026, supporting superconducting, trapped-ion, and neutral-atom hardware. Origin Quantum was added to the U.S. Entity List in May 2024.

Tianyan series. Tianyan-504 went live on the cloud in December 2024. Tianyan-287 (December 2025) is described as fully domestically built and offering cloud-accessible quantum advantage.

Strategic implications. China’s vertically integrated model contrasts with the Western horizontal QOA approach. Both have merits; the Chinese model achieves faster internal coordination at the cost of vendor lock-in. Export controls and Entity List status make Chinese components effectively unavailable to Western government and most regulated-sector customers. Chinese quantum publications may lag actual capability by 18–24 months due to classification review.

Emerging Players and Niche Approaches

Alice & Bob (France). Cat qubit specialists. Demonstrated a one-hour bit-flip time in September 2025 and published an “unfolded” code reducing magic state overhead (August 2025). NVQLink partner. Building bias-preserving cat qubit processors where hardware provides bit-flip protection and software handles phase flips. I cover this approach in my dedicated cat qubit modality article.

AWS (Ocelot chip). Amazon’s quantum hardware team validated the cat-qubit approach with Ocelot in February 2025, demonstrating 100× reduction in error correction overhead compared to conventional approaches.

SEEQC (US). Building single-flux-quantum (SFQ) digital logic controllers that operate at 4 K, inside the cryostat. Demonstrated >99.9% gate fidelity with SFQ control (December 2025). NVQLink controller partner. Partnership with QuantWare for co-integrated SFQ controllers and transmon QPUs.

Atlantic Quantum (US). Pursuing fluxonium-based processors under DARPA’s QBI (Quantum Benchmarking Initiative) program. Fluxonium’s superior coherence and large anharmonicity could enable lower error rates than transmon at the cost of more complex fabrication and control.

Nord Quantique (Canada). Demonstrated bosonic quantum error correction on a single multimode cavity, extending the logical qubit lifetime beyond the physical components. A different approach to hardware-level error protection than surface codes.

Anyon Systems (Canada). Smaller-scale transmon processor company serving the Canadian and North American research market.

D-Wave (Canada). Not a gate-based quantum computer but uses superconducting flux qubits for quantum annealing. The Advantage system has 5,000+ qubits. D-Wave claimed quantum computational advantage with its annealing approach in March 2025. D-Wave’s technology is architecturally distinct from gate-based superconducting computing and does not directly contribute to the CRQC pathway via Shor’s algorithm.

Quantum Error Correction: The Engineering Frontier

If there is one section of this article that matters most for anyone tracking the path to a CRQC, it’s this one. Raw qubit counts are marketing. Error-corrected logical qubits are the engineering reality that will determine when quantum computers can break cryptography.

The core idea: physical qubits are too error-prone to run long computations directly. Quantum error correction spreads a single logical qubit’s information across many physical qubits, using redundancy to detect and correct errors in real time. The dominant scheme for superconducting qubits has been the surface code, which arranges physical qubits on a 2D nearest-neighbor lattice and uses weight-4 stabilizer measurements to catch errors.

The Below-Threshold Moment

Google Willow’s December 2024 result was the first demonstration that the surface code actually works as theory predicted on superconducting hardware. As code distance grew from 3 to 5 to 7, logical error rates dropped exponentially rather than climbing. The error-suppression factor Λ = 2.14 means each step in code distance roughly halves the logical error rate. This is the proof that you can, in principle, make a logical qubit arbitrarily reliable by adding more physical qubits, provided the physical error rate stays below threshold. I analyzed this in detail.

China’s USTC group followed with Zuchongzhi 3.2 crossing the same threshold in late 2025, taking a different approach to the stabilizer measurements.

Beyond the Surface Code

The surface code’s fatal weakness is overhead: at useful error rates, a single logical qubit requires roughly 1,000 physical qubits. That makes a machine capable of running Shor’s algorithm against RSA-2048 a multi-million-physical-qubit affair.

Quantum LDPC codes change the calculus. IBM’s Gross code can encode more logical information per physical qubit, cutting overhead by up to 90%. The tradeoff: qLDPC codes require more complex connectivity than nearest-neighbor, which is why IBM built c-couplers into Loon and why the Kookaburra module is designed around qLDPC-native connectivity. IBM’s concatenated Gross code result in May 2026 reached the teraquop regime (10¹² error-free operations), the strongest evidence yet that qLDPC codes are practically viable.

Real-Time Decoding

Error correction is only useful if you can decode syndromes fast enough to apply corrections before the next error occurs. For surface code on superconducting transmons running at ~1 µs cycle times, the decoder must respond within roughly 10 µs. Riverlane’s Deltaflow 2 (deployed at OQC and Oak Ridge in 2025) and NVIDIA’s NVQLink architecture (3.96 µs measured round-trip latency) make this possible. I discuss the decoder performance bottleneck in my CRQC Quantum Capability Framework.

What This Means for CRQC Timelines

The Gidney 2025 resource estimate for breaking RSA-2048 is ~1,400 logical qubits and ~6.5 billion Toffoli gates. With surface code overhead, that translates to millions of physical qubits. With qLDPC codes at IBM’s projected overhead ratios, the physical qubit requirement shrinks by an order of magnitude. IBM’s Starling (200 logical qubits, 2029) and Blue Jay (2,000 logical qubits, post-2033) are explicitly designed to reach this regime.

I assess these developments in detail in my CRQC Quantum Capability Framework, particularly the capabilities for below-threshold operation, decoder performance, and engineering scale.

Comparison to Other Modalities

Superconducting vs. Trapped Ion

The two modalities furthest along toward fault tolerance. Trapped ions (Quantinuum‘s Helios, IonQ‘s Forte and Tempo) offer all-to-all connectivity, gate fidelities up to 99.921% (Quantinuum’s best, all-pairs), and coherence measured in seconds to minutes. Superconducting qubits counter with gate speeds 1,000× faster (nanoseconds vs. microseconds), simpler scaling via lithographic fabrication, and a more mature integration path into HPC infrastructure via NVQLink.

The comparison that matters is error-corrected operations per second. Consider a concrete example: a superconducting processor running surface code at distance 15 needs ~450 physical qubits per logical qubit and executes QEC cycles at ~1 µs. A Quantinuum-style trapped-ion processor running Skinny Logic codes at a 2:1 ratio executes QEC cycles at ~100 µs. The superconducting machine runs ~20× more logical gates per second, but requires ~225× more physical qubits per logical qubit. Total physical resources (qubit-seconds) per logical gate may actually favor trapped ions, depending on the specific codes and how much parallelism the architecture supports.

There is also a qualitative difference in the QEC codes each modality can run. Trapped ions’ all-to-all connectivity enables high-rate codes (Skinny Logic, iceberg codes) that require non-local stabilizer measurements. Superconducting qubits’ nearest-neighbor connectivity confines them to surface codes unless non-local couplers (IBM’s c-couplers) are added. IBM’s shift to qLDPC codes via the Gross code is an attempt to close this gap, but it requires hardware changes (new coupling elements, higher connectivity) that are not yet deployed at scale.

The honest assessment: neither modality has a clear overall advantage. The winner will be determined by engineering execution over the next five years. I cover trapped-ion quantum computing in a separate modality article.

Superconducting vs. Neutral Atom

Neutral-atom systems (QuEra, Pasqal, Atom Computing) have caught up faster than most predicted. QuEra’s 96 verified logical qubits on 448 physical atoms (November 2025, Nature) and 2:1 physical-to-logical ratios with qLDPC codes (April 2026) represent efficiency numbers that surface-code superconducting systems cannot currently match.

Neutral atoms have three structural advantages worth unpacking. First, they operate at room temperature (no dilution refrigerator), eliminating the entire cryogenic infrastructure stack and its helium-3 supply chain risk. Pasqal’s Orion fits in a standard server rack at 3 kW. Second, their connectivity is reconfigurable: optical tweezers can rearrange atom positions between circuit layers, enabling non-planar code layouts without fixed hardware routing. Third, raw atom count scales more readily (Atom Computing demonstrated 1,180 trapped atoms in 2023; Caltech demonstrated a 6,100-atom tweezer array in September 2025).

The superconducting counter-arguments: gate speeds are faster by 100–1,000× (ns vs. µs for Rydberg gates), mid-circuit readout is more mature (neutral-atom readout requires fluorescence imaging that currently destroys neighboring atoms’ states), and the superconducting QOA ecosystem lets integrators assemble custom systems from components. Neutral atoms also suffer from atom loss during computation: atoms occasionally escape the tweezer traps, reducing the available qubit count mid-circuit. Harvard/QuEra’s erasure-detection techniques mitigate this by converting atom loss into a detectable error, but it remains an overhead that superconducting qubits do not face.

Superconducting vs. Silicon Spin

Silicon spin qubits share the superconducting modality’s CMOS fabrication heritage but encode information in electron or hole spins in quantum dots on isotopically purified ²⁸Si substrates. Diraq‘s September 2025 demonstration of >99% two-qubit fidelity on industrially fabricated 300 mm wafers validated the CMOS-compatible mass-production thesis. Silicon spin qubits can operate at ~1 K (versus 10–20 mK for transmons), relaxing cryogenic requirements and enabling the use of helium-4-only cryostats that avoid the He-3 supply constraint.

The qubit count is years behind: the largest demonstrated silicon spin processors have ~12 qubits versus 1,000+ for superconducting. The first logical operations on silicon spin qubits were demonstrated in March 2026, and the first quantum error detection in January 2026. But the long-term cost argument is compelling. If silicon spin qubits achieve the same yield curves as classical transistors on 300 mm CMOS lines, the cost per qubit could drop by orders of magnitude compared to superconducting circuits fabricated in specialized quantum fabs. A recent Nature Reviews assessment of CMOS-spin qubit compatibility (April 2026) is the definitive reference on where this thesis stands. Silicon is a longer-term play, but one with a potentially transformative cost-per-qubit advantage.

Superconducting vs. Photonic

Photonic quantum computers (PsiQuantum, Xanadu, Quandela) encode qubits in light, operating largely at room temperature with cryogenics needed only for single-photon detectors. PsiQuantum‘s Omega chipset (February 2025, Nature) achieved 99.98% state preparation and measurement and 99.72% two-qubit fusion gate fidelity, fabricated at GlobalFoundries’ commercial semiconductor fab in Malta, NY.

The photonic approach scales through fundamentally different physics. Entangling gates are probabilistic (fusion operations succeed with some probability and fail with a detectable “erasure”), requiring measurement-based or fusion-based architectures that consume large numbers of photonic resources per logical qubit. PsiQuantum’s fusion-based quantum computing (FBQC) architecture addresses this by using error-correction codes designed specifically for erasure-dominant noise, which can tolerate the probabilistic gate failures. QuiX Quantum achieved the first below-threshold error mitigation in photonic quantum computing in April 2026, a significant milestone.

Photonic systems are not yet competitive with superconducting qubits for gate-model computation, but they hold two structural advantages. First, photons are the natural carrier for quantum networking: connecting two superconducting processors requires transduction from microwave to optical frequencies, while photonic processors communicate natively via optical fiber. Second, photonic architectures can leverage existing semiconductor fabs (PsiQuantum at GlobalFoundries, Xanadu at its own facility) without the cryogenic fabrication constraints of superconducting circuits. PsiQuantum’s million-qubit compute centers in Brisbane and Chicago are under construction, representing a bet that fusion-based photonic computing can scale faster than any matter-qubit approach once the fab pipeline is running.

Advantages

Speed. Superconducting qubits have the fastest gates of any leading modality. Single-qubit gates in 10–20 ns, two-qubit gates in 20–100 ns (OQC demonstrated 25 ns CZ at 99.8% fidelity), readout in ~500 ns. This translates to surface-code cycle times around 1 µs (Google Willow: 1.1 µs), which determines how quickly the processor can detect and correct errors. The cycle-time advantage compounds over long computations: a superconducting processor completes an error-correction round in the time a trapped-ion system completes a single two-qubit gate. This speed advantage extends beyond raw throughput. It also means superconducting processors are more forgiving of idle noise, because qubits spend less time waiting between operations.

Fabrication maturity. These are lithographically defined circuits manufactured using processes adapted from the semiconductor industry. QuantWare is building KiloFab, a dedicated QPU fabrication facility in Delft targeting 20× production capacity increase. IBM runs production at its own facilities and has fabricated processors up to 1,121 qubits on a single die. Google, Rigetti, and IQM all fabricate in-house or at partner foundries. The fabrication pipeline is more mature and repeatable than for any other modality. Chip-to-chip reproducibility is improving: QuantWare ships every QPU with pre-delivery cryogenic characterization (T₁, T₂R, T₂e, frequencies), and customers can compare their measured values against the vendor datasheet. That level of quality documentation is nascent in other modalities.

QOA component availability. Superconducting is the only modality where an independent integrator can assemble a working quantum computer from commercially available components purchased from different vendors. The bill of materials is well-defined: QPU from QuantWare or Rigetti, cryostat from Bluefors or Maybell or Oxford Instruments, control electronics from Qblox, Quantum Machines, or Zurich Instruments, cryogenic wiring from Delft Circuits (Cri/oFlex), calibration software from Q-CTRL or QuantrolOx, and HPC integration via NVQLink. The Q-PAC system in Denver went from concept to cloud-accessible operation in five months. The Tuna-5 in Delft and the Quantum Utility Block (QUB) reference architecture from QuantWare + Q-CTRL + Qblox provide pre-validated blueprints at multiple scales. I cover this supply chain in depth in my building a quantum computer series.

HPC integration. NVQLink, announced by NVIDIA at GTC Washington DC in October 2025 with 17 QPU builders and 9 U.S. national laboratories, provides 400 Gb/s GPU-QPU throughput at <4 µs measured latency (arXiv:2510.25213). All three major control electronics vendors support NVQLink. The Quantum Resource Management Interface (QRMI) makes QPUs Slurm-schedulable alongside CPUs and GPUs. This integration stack means a superconducting quantum computer can function as a co-processor in an existing HPC environment, accessible through standard job submission interfaces. The LRZ/IQM deployment, documented in arXiv:2509.12949, provides the reference architecture. I discuss the practical details in my HPC integration deep dive.

Error correction track record. Google Willow is the only platform that has demonstrated below-threshold surface code scaling. IBM’s qLDPC work on the Gross code is the most advanced high-rate code demonstration on real hardware. USTC’s Zuchongzhi 3.2 independently crossed the error correction threshold. These three results, all on superconducting transmons, represent the strongest empirical evidence that fault-tolerant quantum computing is achievable. No other modality has three independent groups demonstrating below-threshold error correction on hardware (though Quantinuum’s trapped-ion results with Skinny Logic codes are approaching equivalent significance).

Disadvantages

Cryogenic infrastructure. Every superconducting quantum computer requires a dilution refrigerator maintaining 10–20 mK. A Bluefors LD450sl costs $700k–$1M with a ~4-month lead time; an XLD1000sl runs $1.5M–$2.5M; a KIDE-class system supporting 1,000+ qubits costs $5M–$10M. These systems weigh 750–7,000 kg, take 1–7 days to cool down depending on payload, and require helium-3, a strategically constrained isotope derived primarily from nuclear weapons tritium decay. Terrestrial He-3 supply runs roughly 22,000–30,000 L/year against estimated demand of 40,000–60,000 L/year. An XLD1000sl holds ~40 L of He-3 at ~$100,000 at current prices ($2,500/L). Bluefors signed a lunar He-3 offtake agreement with Interlune in September 2025, but delivery before 2029 is technologically aggressive. I cover these constraints in detail in my cryogenic infrastructure deep dive and my analysis of what a quantum computer costs.

Limited connectivity. Transmons on a planar chip typically couple only to their nearest neighbors on a square lattice. Running algorithms that require long-range qubit interactions means routing through chains of SWAP gates, consuming time and adding errors. Each SWAP costs three CZ gates. IBM’s c-couplers and IQM’s Constellation hexagonal topology address this, but at the cost of fabrication complexity. Neutral atoms and trapped ions, with their reconfigurable and all-to-all connectivity respectively, have a structural advantage here. This connectivity limitation also determines which error-correcting codes can run efficiently: surface code maps naturally onto square lattices, but the more efficient qLDPC codes require non-local connections that planar architectures must engineer in.

Error correction overhead. Despite QEC progress, the physical-to-logical qubit ratio remains demanding. Surface code at distance 20 (needed for cryptographically relevant computations) requires roughly 800 physical qubits per logical qubit. IBM’s Gross code promises to cut that by 90%, but the engineering to implement qLDPC-native connectivity at scale is unproven at production volumes. Compare this to Quantinuum’s Skinny Logic codes on trapped ions, which achieved 2:1 physical-to-logical ratios (98 physical → 48 logical qubits) by exploiting all-to-all connectivity.

Calibration drift. Superconducting qubits are analog devices that require continuous recalibration. Qubit frequencies shift with trapped magnetic flux, TLS defects wander, and cross-talk couplings change over time. A 20-qubit system needs recalibration every 1–6 hours for frequencies and gate amplitudes, with full tune-ups weekly to monthly. The IQM/LRZ team reports a quick recalibration cycle of ~40 minutes and full recalibration of ~100 minutes for their 20-qubit machine. Once tuned, systems can run 100+ days unattended between major recalibrations. Automated calibration platforms (Q-CTRL Boulder Opal Scale-Up, QuantrolOx Quantum EDGE, QM QUAlibrate) mitigate this, but the underlying drift is an intrinsic property of Josephson circuits that atomic-qubit systems do not suffer at the same scale.

I/O wiring bottleneck. Every qubit requires multiple RF and DC lines from room temperature to millikelvin. Conventional coaxial cables top out at ~168 channels per cryostat loader. Each cable segment adds thermal load: running a 100-qubit setup with naive coaxial wiring can exhaust the 100 mK cooling power budget on attenuators alone. Delft Circuits’ Cri/oFlex (256 channels per 108 mm port today, targeting 4,096 by 2029) and Bluefors’ High-Density Flex Wiring (240 channels per port) address this, but the I/O wall remains the binding constraint on qubit scaling beyond ~500 per cryostat. The long-term solution is cryo-CMOS: placing control electronics inside the cryostat at 4 K. Intel’s Horse Ridge II, SEEQC’s SFQ controllers, and Diraq’s mK-CMOS co-integration are all working toward this, but cryo-CMOS will not replace room-temperature control racks before ~2028.

FPGA supply chain. All three major control electronics platforms and Riverlane’s Deltaflow decoder rely on AMD/Xilinx RFSoC FPGAs. These compete for allocation with defense, telecom, and AI workloads. Allocation conflicts have already delayed delivery schedules.

Impact on Cybersecurity

This section is not theoretical. The superconducting qubit community is on a trajectory that will, if current trends continue, produce the hardware capable of breaking RSA and ECC. I assess that trajectory through my CRQC Quantum Capability Framework, and the conclusion is that every major capability dimension required for a CRQC is advancing simultaneously on superconducting hardware.

The Threat Model

A cryptographically relevant quantum computer running Shor’s algorithm can factor large integers and compute discrete logarithms in polynomial time. This breaks RSA, Diffie-Hellman, and elliptic curve cryptography. The Gidney 2025 estimate puts the cost of breaking RSA-2048 at ~1,400 logical qubits and ~6.5 billion Toffoli gates, down from the 20 million physical qubits estimated in 2021. For ECC (specifically P-256 ECDLP), the Chevignard/Fouque/Schrottenloher EUROCRYPT 2026 result (which I covered in my analysis of the 1,000-qubit ceiling) estimates 1,193 logical qubits. Google’s Babbush team published a separate ECDLP resource estimate reducing qubit requirements by roughly 10× from prior estimates.

These numbers are declining. Every year, algorithmic improvements shrink the estimated resources for cryptanalysis. That is not a sign of imminent doom; it is a sign that the gap between current hardware and cryptographically relevant hardware is closing faster than most people assume.

Where Superconducting Hardware Sits on the CRQC Path

Map the current state against my CRQC framework capabilities:

Below-threshold operation: Demonstrated (Google Willow, USTC Zuchongzhi 3.2). This box is checked.

Quantum error correction: Surface code demonstrated; qLDPC codes reaching teraquop regime (IBM). In progress.

Decoder performance: Sub-10-µs real-time decoding demonstrated via NVQLink. Sufficient for current code sizes; must scale.

Magic state production: Not yet demonstrated at scale on superconducting hardware. IBM’s Starling roadmap targets magic state injection across modules in 2028.

Continuous operation: Hours to days of continuous operation demonstrated (LRZ reports 100+ days between major recalibrations). Must extend to the weeks-to-months required for cryptanalytic computations.

Engineering scale: QuantWare’s KiloFab and IBM’s Poughkeepsie data center represent the first dedicated manufacturing facilities for superconducting quantum hardware at scale.

No single capability is a showstopper in isolation. The challenge is integrating all of them simultaneously, at scale, continuously. That integration is an engineering problem, not a physics problem. Which is precisely why organizations need to act now rather than waiting for certainty.

What Should You Do?

If your organization uses RSA, Diffie-Hellman, or ECC (and it does), the response is not to panic about superconducting qubit progress. It’s to begin PQC migration. The NIST-standardized algorithms, ML-KEM (FIPS 203), ML-DSA (FIPS 204), and SLH-DSA (FIPS 205), are available now. The Harvest Now, Decrypt Later threat means data encrypted today can be stored and decrypted once a CRQC arrives. And the real deadline isn’t Q-Day itself: regulators, insurers, investors, and clients are setting their own quantum deadlines that arrive years before any quantum computer breaks a key.

Future Outlook

The near-term trajectory of superconducting qubits is, for the first time, predictable in its broad strokes. Not in the “quantum computing will change everything” sense of hype, but in the concrete, engineering-milestone sense that I find more useful.

2026–2027: The modular era begins.

IBM delivers Kookaburra, the first fault-tolerant module integrating logic and memory via qLDPC codes with c-couplers for non-local connectivity. Cockatoo follows in 2027, linking two Kookaburra modules via l-couplers. These processors move IBM from “demonstrating QEC” to “operating in QEC mode” as a sustained engineering practice. IBM expects to demonstrate quantum advantage on Heron-class hardware by end of 2026 through hybrid quantum-classical computations with HPC partners. The Nighthawk processor line continues for NISQ workloads in parallel.

IQM deploys 150-qubit Radiance and Halocene systems at LRZ (completing Euro-Q-Exa) and VTT Finland, bringing European superconducting quantum infrastructure to scale. The 300-qubit VTT system (2027) will be purpose-built for QEC research. IQM’s $1.8 billion SPAC listing (announced February 2026) provides capital for the Constellation architecture scaling beyond 1,000 qubits.

QuantWare brings KiloFab online, increasing production capacity by 20×. Contralto and Tenor QPUs ship to the expanding QOA market. The Quantum Utility Block reference architecture matures into a standard integration recipe. VIO-40K reservations are open for 2028 delivery.

Google is the most opaque major player about near-term chip plans. The successor to Willow is in development but unannounced. Google’s focus remains on quality-first scaling: pushing error rates down and code distances up rather than maximizing qubit count. Expect continued QEC demonstrations at increasing code distances on Willow-class hardware.

Rigetti targets a 100+ qubit chiplet-based system with 99.5% median two-qubit fidelity by end of 2025, and continued fidelity improvements through 2026. Rigetti’s modular multi-chip architecture (pioneered with Aspen-M in 2021) positions it for scaling via chiplet tiling rather than monolithic dies.

OQC launches Genesis, introducing Dimon dual-rail qubits with a claimed 1:1 physical-to-logical qubit ratio. If the performance claims hold under independent benchmarking, this would be a significant architectural advance. OQC’s long-term Titan roadmap targets 200 logical qubits within 2,000 lattice sites on a 100 mm wafer-scale processor.

Coherence records will continue to climb as tantalum-on-sapphire fabrication and surface-treatment techniques propagate through the vendor ecosystem. The 1,000-qubit ceiling is overcome not by building bigger chips but by connecting smaller ones.

2028–2029: The fault-tolerance threshold.

IBM’s Starling targets 200 logical qubits running 100 million operations at a new quantum data center in Poughkeepsie, NY. This is the system designed to prove that fault-tolerant quantum computing works at a scale where it starts to produce results beyond classical simulation. QuantWare’s VIO-40K aims for 10,000 physical qubits on an open architecture, which at a 10:1 qLDPC ratio would yield ~1,000 logical qubits. If either target is achieved, the first computations that are out of reach for any classical machine become plausible.

Cryo-CMOS control begins to replace room-temperature rack electronics. Intel’s Horse Ridge III (in development), SEEQC’s SFQ controllers, and QuantWare-SEEQC co-integration are the leading programs. Moving control electronics inside the cryostat at 4 K eliminates the I/O wiring bottleneck that currently limits superconducting systems to ~500 qubits per cryostat with conventional cabling. This architectural shift is essential for the 10,000-qubit regime.

NVQLink matures into the standard HPC-quantum interconnect. Real-time QEC decoding on GPU (NVIDIA GB200/GH200) becomes routine.

2030–2033: The CRQC window.

This is the window where a CRQC becomes plausible if error correction overhead reductions hold and manufacturing scales. IBM’s Blue Jay targets 2,000 logical qubits and 1 billion operations post-2033. QuantWare’s VIO architecture targets paths beyond 10,000 qubits toward million-qubit systems, though these are very early-stage projections.

Whether superconducting transmons still dominate at this point is an open question. Fluxonium’s superior coherence and anharmonicity may make it the preferred qubit for fault-tolerant processors where per-gate error rate matters more than gate speed. Cat qubits (Alice & Bob, AWS Ocelot) offer hardware-level bit-flip protection that could reduce QEC overhead by 100×. Hybrid approaches combining transmons for fast operations with cavity modes for long-lived memory may prove optimal.

The competitive question is whether trapped ions (Quantinuum‘s Apollo targets universal FTQC by 2029–2030) or neutral atoms (QuEra‘s qLDPC-enabled scaling) close the gap. What’s not an open question is whether the underlying physics works: the below-threshold demonstrations in 2024–2025 settled that.

The future of superconducting qubits is not a single company’s roadmap. It’s an engineering discipline with a growing vendor ecosystem, standardizing interfaces, and demonstrated performance at every major milestone short of fault tolerance itself.

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