Building a Superconducting Quantum Computer

Introduction

The chandelier photograph has become the defining image of quantum computing: nested gold and silver thermal stages descending from a top plate, threaded with coaxial cables, terminating in a tiny chip at the bottom. It looks like a piece of high-tech sculpture. It is, in fact, an engineering problem dense enough to occupy a team of specialists for months.

A superconducting quantum computer is, at its core, a set of microwave resonant circuits cooled to 10–20 millikelvin (roughly 150 times colder than deep space) so that quantum-mechanical effects dominate over thermal noise. The qubit itself is a transmon: a nonlinear LC oscillator formed by a Josephson junction shunted by a large capacitor. Qubits are addressed and coupled via microwave pulses at 4–8 GHz. Two-qubit gates are implemented via tunable couplers (QuantWare, Google, Rigetti) or fixed-coupling cross-resonance (IBM).

The physics of the transmon is well understood. The engineering of building a working multi-qubit system from commercially available components is not a textbook exercise. It is a multi-vendor integration project that spans cryogenic engineering, microwave signal integrity, vacuum science, pulse-level quantum control, calibration science, and classical IT infrastructure. This article covers that integration, step by step, from the moment you commit to a superconducting build to the moment your system accepts its first external user job.

For the physics of how transmon qubits work, see my Quantum Computing Modalities series. For who makes the components, see What It Takes to Build a Quantum Computer. For the broader context of why this modular approach is now possible, see the capstone article in this series.

Choosing your QPU

The QPU selection determines everything downstream: the cryostat specifications, the control electronics configuration, the wiring channel count, and the calibration sequence. For a superconducting build in 2026, two vendors sell standalone QPU components into the Quantum Open Architecture market.

QuantWare (Delft, Netherlands) is the dominant QOA QPU supplier, with over 50 customers across 20 countries and a product line covering four qubit counts. The Soprano-D5 is a 5-qubit entry chip at approximately €60K. The Contralto-D21 provides 21 qubits at approximately €300K. The Contralto-A3 is a 17-qubit QEC-optimized variant with tunable couplers, Purcell filters, and a distance-3 surface-code layout; it won the Quantum Effects 2025 Best Quantum Hardware award and powers the Q-PAC deployment. The Tenor-D64 delivers 64 qubits and is deployed at Naples. All Gen-D processors ship with pre-delivery cryogenic characterization: T1, T2-Ramsey, T2-echo, and qubit frequencies measured in QuantWare’s own cryostat.

QuantWare’s vendor-typical performance for the Gen-D line: ~60 µs average coherence, 99.9% single-qubit gate fidelity, 99.7% two-qubit gate fidelity, 97.5% readout fidelity with the Crescendo-S TWPA. These are device-typical results, not per-chip guaranteed minimums. Every chip varies. Measure your own.

Rigetti (Berkeley, US) sells the Novera, a 9-qubit transmon QPU in a 3×3 lattice with tunable couplers. Starting price is approximately $900K for the QPU component; complete systems with upgrade packages have been reported at ~$2.85M based on September 2025 purchase orders. Representative qubit metrics: T1 = 45.9 µs, T2-echo = 25.5 µs. The Novera ships in 4–6 weeks, substantially faster than QuantWare’s 3–6 month lead time. It is compatible with any cryostat providing at least 290 mm MXC diameter and at least 14 µW cooling power at 20 mK.

The decision framework. For a first superconducting system focused on education, algorithm development, or hardware familiarization, the QuantWare Soprano-D5 or Rigetti Novera are the entry points. For serious research, QEC experiments, or the start of a commercial quantum service, the QuantWare Contralto-A3 (17 qubits, QEC-ready) is the recommended specification. For scaling toward computational utility, the Tenor-D64 is the largest QOA QPU available today, with QuantWare’s VIO-40K architecture targeting 10,000 qubits (first shipments 2028, funded by the $178 million Series B).

Other QPU builders sell integrated systems, not standalone components: IBM (Heron 156 qubits), Google (Willow 105 qubits), IQM (Radiance 54 qubits at Euro-Q-Exa), OQC (Toshiko 32 qubits), Alice & Bob (cat qubits). These are relevant as competitive reference points and as vertically integrated alternatives to the QOA build described here, but their QPUs are not available as standalone procurement items.

Choosing your cryostat

The dilution refrigerator is the most expensive, longest-lead, and physically largest component. It is also the component you are least likely to replace: a well-chosen cryostat serves a decade or more, while QPUs and control electronics are upgraded on shorter cycles.

The dedicated cryogenic infrastructure article in this series covers the full vendor comparison, helium-3 supply chain, and the I/O wiring wall in depth. Here, the focus is on the selection criteria that affect the superconducting build specifically.

Bluefors LD450sl (previously LD400sl, renamed March 2026). The standard research workhorse. Base temperature below 10 mK. Over 450 µW cooling power at 100 mK. Preconfigured systems ship in approximately 4 months, making the LD the fastest-available option for a new build. Supports up to ~30 qubits with conventional wiring, more with Cri/oFlex. The “sl” suffix denotes side-loading capability for wiring access. Price range: $700K–$1M. Best for: budget-constrained first systems, fast-turnaround research deployments, systems up to 30 qubits.

Bluefors XLD1000sl. The mid-to-large workhorse. Over 1,000 µW cooling power at 100 mK. Dual pulse-tube cryocoolers. Pre-installed Cri/oFlex integration through the Bluefors/Delft Circuits partnership. Lead time: 6–12 months. Holds approximately 40 liters of helium-3 (~$100K at current prices). Price range: $1.5M–$2.5M. Best for: 30–400 qubit builds, QEC research, systems that need headroom for QPU upgrades.

Maybell Quantum Big Fridge (Denver, US). Over 1,000 µW cooling power at 100 mK. Approximately 130-liter sample volume. Over 3,400 cm² MXC plate area. Integrated Minus K Technology negative-stiffness vibration isolators rated below 0.5 Hz. Integrated LF CryoTrace flex ribbon (MIT Lincoln Lab license). The Big Fridge eliminates scroll pumps, acid-flux solder, rubber gaskets, and KF flanges in favor of welded and metal-to-metal joints, a design philosophy aimed at reducing maintenance frequency. Lead time: approximately 6 months. Price range: $1.5M–$3M. Best for: US sovereign supply chain requirements, builds where integrated vibration isolation is valued, 30–200 qubit range.

Oxford Instruments Proteox LX (Abingdon, UK). Modular dilution refrigerator with rapid sample exchange. Over 450 µW class cooling power at 100 mK. Oxford reports a 50% lead-time reduction from prior baselines via a factory-reconfiguration program (informally 5–8 months). Best for: academic groups needing frequent QPU swaps, multi-project environments.

Bluefors KIDE. The industrial platform. Over 3,000 µW cooling power at 100 mK from three independent cooling units. Hexagonal chamber approximately 3 m tall × 2.5 m diameter. 1.6 m² MXC flange. Over 1,000 qubits supported. 24 side-loading ports plus top-loading. Up to 500 kg payload. First 18 systems shipped to the AIST G-QuAT center in Tsukuba, Japan (May 2025); used inside IBM Quantum System Two. Price range: $5M–$10M class. Long-life cold trap enables continuous operation up to 3 years between full warm-ups. Lead time: 6–12 months. Best for: 400–1,000+ qubit builds, national laboratory installations.

The build-for-the-next-system principle. If your roadmap targets 100+ qubits within five years, do not buy an LD450sl to save money today. The cost difference between an LD and an XLD is roughly $800K–$1.5M. The cost of operating an undersized cryostat for two years and then replacing it (including a second facility remediation, a second cool-down commissioning, and weeks of downtime during the swap) will exceed that differential. Buy the XLD1000sl or Big Fridge from the start. Specify side-loading from day one. Install helium recovery infrastructure at the same time.

The signal chain: from room temperature to 10 millikelvin

This is the section that separates a quantum computing article from a quantum computing engineering guide. The signal chain determines whether your QPU performs to its vendor-characterized specifications or sits in a very expensive refrigerator producing noise.

Every transmon qubit requires at least three types of signal lines connecting room-temperature electronics to the millikelvin chip: drive lines (microwave pulses that implement gates), readout lines (microwave probes that measure the qubit state), and flux lines (baseband DC/pulse signals that tune qubit frequencies, for tunable-coupler architectures). A 20-qubit system with tunable couplers can require 80–120 distinct cryogenic signal paths.

The drive line

The drive line carries precisely shaped microwave pulses (typically 4–8 GHz, 20–50 ns Gaussian or DRAG envelopes) from room-temperature electronics to the qubit. The fundamental design problem: room-temperature electronics operate at 300 K. The qubit operates at 10–20 mK. The thermal noise from 300 K electronics would immediately dephase the qubit if it arrived unattenuated.

The solution is staged attenuation across the cryostat’s thermal stages, totaling approximately 62 dB from room temperature to QPU. The canonical high-fidelity drive line for an XLD-class system:

At room temperature, the signal originates from a Qblox QCM-RF module (direct synthesis at 0.4–18.5 GHz, eliminating the need for standalone local oscillators in most transmon work), a Quantum Machines OPX+ MW-FEM, or a Zurich Instruments SHFQC+ (DC to 8.5 GHz, integrated signal generation and analysis). If using standalone sources, Rohde & Schwarz SGS100A or Keysight E8267D local oscillators feed IQ mixers (Marki Microwave IQ-0618LXP or equivalent).

From room temperature to 50 K, stainless-steel semi-rigid coax (Coax Co. SC-086/50-SS-SS or MicroCoax UT-085-SS, 50 Ω, ~1.5 dB/m at 6 GHz) carries the signal down, passing through a 20 dB fixed attenuator (XMA 2082-6426-20) and a low-pass filter with ~12 GHz cutoff (K&L Microwave 6L250-12000) at the 50 K stage. Both components are thermalized to the 50 K flange.

From 50 K to 4 K, the cable transitions to NbTi superconducting coax (Coax Co. SC-086/50-NbTi-NbTi or Keycom NbTi), which goes superconducting below ~9 K and exhibits near-zero loss. A 6 dB attenuator sits at 4 K. Another 6 dB attenuator sits at the still (~700 mK).

At the cold plate (~100 mK), a 10 dB attenuator joins an eccosorb infrared filter. These IR filters are critical: they absorb infrared photons above ~100 GHz that would otherwise generate quasiparticles in the superconducting QPU, degrading T1. Many groups build these in-house; commercial options include QDevil QFilter and Bluefors’ eccosorb filter. A second IR filter sits at the mixing chamber (~10 mK), along with the final 20 dB attenuator and a DC block (Marki Microwave DBL-0218) to prevent ground loops.

Total attenuation budget: 20 + 6 + 6 + 10 + 20 = 62 dB. Room-temperature noise at 300 K corresponds to ~6.2 × 10⁻²¹ W/Hz. After 62 dB attenuation, residual noise power drops to ~4 × 10⁻²⁷ W/Hz, well below the single-photon energy at 5 GHz (~3.3 × 10⁻²⁴ J). The margin accommodates cable losses and imperfect thermalization.

The readout chain

The readout chain runs in the opposite direction: from the QPU back up to room temperature. The challenge is amplifying the qubit’s feeble microwave signal (a few photons at 5–8 GHz) without adding noise that destroys the measurement fidelity.

At the mixing chamber, the signal passes through an on-chip Purcell filter (integrated into the QPU design on QuantWare Contralto-A and Rigetti Novera) and into a traveling-wave parametric amplifier (TWPA). The TWPA is the near-quantum-limited first amplification stage, providing roughly 20 dB of gain across a 4–8 GHz bandwidth. The newest commercial option is Silent Waves’ Zephyr (launched March 2026), which integrates the TWPA and pump coupler into a single device, reducing the component count and footprint at the MXC stage. VTT’s TWPA-1A (Finland) is the established alternative. Pricing: $15K–$50K per device. The TWPA requires a dedicated pump line from room temperature carrying a pump tone (typically ~11 GHz, +15 to +20 dBm at the pump port) with its own lighter attenuator chain (~30 dB total) and a directional coupler at MXC.

After the TWPA, the signal passes through a circulator (Low Noise Factory CICIC4_12A or Quinstar QCY-060400CM00, 4–12 GHz, >18 dB isolation, <0.5 dB insertion loss) that prevents back-action from reaching the qubit. A second circulator sits at the cold plate. At 4 K, a HEMT (high electron mobility transistor) low-noise amplifier (Low Noise Factory LNC4_8C, the market leader, or Cosmic Microwave Technology CITLF3) provides the first high-gain amplification stage at approximately 40 dB with 2–4 K noise temperature. The signal then travels via stainless steel coax to the room-temperature digitizer (Qblox QRM-RF, QM OPX+, or Zurich SHFQA), where it is demodulated and processed.

The HEMT and TWPA are the two most difficult-to-replace components in the signal chain. Lead times can stretch to months. Keep at least one spare of each on site.

The flux line

For tunable-coupler architectures (QuantWare Contralto-A, Rigetti Novera), each tunable qubit and each tunable coupler requires a flux line carrying baseband DC and fast pulse signals (DC to ~500 MHz). These lines use twisted-pair or filtered DC loom, or the DC channels on Cri/oFlex assemblies. Attenuation is lighter than the drive line. At the MXC, a low-pass filter with approximately 1 GHz cutoff and an eccosorb/copper-powder filter suppress high-frequency noise from coupling into flux-sensitive qubits.

Why Cri/oFlex changes the integration calculus

For systems above approximately 32 channels, Delft Circuits’ Cri/oFlex replaces the entire per-stage coax-and-discrete-attenuator assembly. Each Cri/oFlex ribbon carries 8 channels on NbTi superconducting stripline printed on polyimide, 0.3 mm thick. Attenuators, low-pass filters, and IR filters are integrated directly into the flex structure. Thermal anchoring is achieved by clamping the ribbon at each cryostat stage.

The bill of materials simplifies substantially. Instead of roughly 15 discrete components per qubit per line (coax segments, attenuators, filters, connectors, thermal anchors), the integrator specifies Cri/oFlex assemblies by channel count and attenuation profile. Delft Circuits provides custom attenuation profiles per project. The Bluefors/Delft Circuits integration pre-installs Cri/oFlex in XLDsl-series fridges: each side-loader supports up to 256 high-frequency lines in configurations of 64, 128, or 256 channels, allowing up to 1,536 lines in an XLDsl system and 512 in an LDsl system.

The Cri/oFlex roadmap (from Delft Circuits’ September 2025 publication): 1,024 channels per loader by 2027. 4,096 by 2029. This roadmap defines the scaling ceiling for superconducting quantum computers more directly than any QPU roadmap.

An integrator starting a new build in 2026 should not accept a coax-only wiring design for any system above 20 qubits. The upgrade path from coax to flex requires a full warm-up, complete rewire, and cool-down cycle. That means 2–4 weeks of downtime and the risk of disrupting a working system. Specify flex from day one.

The integration sequence: empty lab to first qubit signal

The following timeline synthesizes the Q-PAC deployment data, the IQM/LRZ operational experience (arXiv:2509.12949), and Applied Quantum’s playbook. Timelines assume a superconducting system in the 17–64 qubit range with automated calibration.

Phase 0: Site preparation and procurement (months 0–3, parallel tracks)

Two workstreams run simultaneously. For the complete facility design specification, including a reference floor plan, vibration survey methodology, and modality-by-modality comparison of site requirements, see the dedicated facility preparation guide. The summary for a superconducting build:

The site preparation track conducts the facility survey: 25+ hours of vibration accelerometer data measured against VC-A or stricter criterion, EMI spectrum analysis across 4–8 GHz, DC and AC magnetic field mapping, power quality analysis (THD, sags, swells, 3-phase balance), floor loading verification (minimum 1,000 kg/m² at the cryostat location), cooling infrastructure assessment (chilled water at 15–25°C, 10–30 L/min, 4–6 bar for the pulse-tube compressor), and ceiling height confirmation (minimum 3 meters for an XLD plus top-loading wiring tree with overhead crane access).

Remediation work begins immediately after the survey: vibration isolation pad or slab reinforcement, EMI shielding (Faraday cage or shielded enclosure, replacement of fluorescent lighting with low-noise LED arrays on DC drivers, star-topology grounding), dedicated 3-phase 63 A panel with conditioned power (total harmonic distortion below 1%), online double-conversion UPS sized for at least 20 minutes of full load, chilled-water plant installation, and helium recovery system installation (Quantum Technology Corp HR3/HRHP series).

The procurement track runs in parallel: cryostat order (longest lead item), QPU order, control electronics order (with FPGA allocation confirmed in writing), Cri/oFlex wiring order, calibration software license, and NVQLink GPU node procurement.

Phase 1: Cryostat installation and verification (month 3–4)

The cryostat arrives and vendor field-service personnel install it: positioning, leveling, pumping and compressor commissioning, gas-handling system connection, first empty cool-down to base temperature. A preconfigured Bluefors LD system reaches base temperature (below 10 mK) in 24–72 hours; an XLD with full payload takes 3–7 days.

Phase 1 verification: compare actual cooling power at 20 mK, 100 mK, and 4 K against the vendor datasheet curves. Check that MXC reaches below 15 mK. Confirm still temperature is approximately 700 mK, cold plate approximately 100 mK, 4 K stage below 4.2 K. If any stage misses its target, the usual causes are helium-3/helium-4 mixture contamination, a blocked impedance in the dilution circuit, or pulse-tube degradation. Resolve before proceeding.

Phase 2: Wiring tree installation and verification (months 4–5)

With the cryostat cold and verified, warm it back up (2–4 days, controlled) and install the wiring tree. For a Cri/oFlex-equipped system, this means loading flex ribbon assemblies through the side-loading ports with the specified attenuation profiles, installing the TWPA at the MXC stage, mounting the HEMT amplifier at 4 K, placing circulators and isolators at MXC and cold plate, and installing magnetic shielding (mu-metal Cryoperm cans from Vacuumschmelze or Amuneal A4K for DC fields, superconducting niobium or lead cans for high-frequency rejection).

For a conventional coax system, this means threading individual coax segments between every thermal stage, installing discrete attenuators and filters at each stage, and ensuring every connector is properly torqued and thermalized. This takes substantially longer and is more error-prone.

Before installing the QPU, verify the wiring with a dedicated cool-down cycle. At room temperature: DC continuity check on all RF lines. Time-domain reflectometry (TDR) on all RF lines, verifying no impedance discontinuities greater than 5 Ω from 50 Ω. At base temperature: VNA S-parameter sweep confirming S11 below -15 dB across 4–8 GHz for all drive and readout lines, and S21 (transmission) consistent with expected attenuation at each stage.

This verification cool-down catches wiring faults before the QPU is installed. Discovering a broken cable or a poorly thermalized attenuator after a QPU cool-down wastes 2–4 weeks (warm-up, fix, cool-down again).

Phase 3: QPU installation (days)

Warm the cryostat. Mount the QPU sample holder on the MXC plate. The sample holder is a machined copper carrier with a printed circuit board and SMA/SMP connectors (QDevil QBoard from the Quantum Machines subsidiary, QuantWare’s custom carrier, or an in-house design). Oxygen-free copper braids provide thermal contact between the sample holder and the MXC plate. Install the magnetic shield stack: innermost superconducting niobium or lead can for high-frequency field rejection, outermost mu-metal can for DC field rejection. Verify room-temperature DC continuity on all flux and DC bias lines. This step takes 2–4 hours for an experienced team.

Phase 4: Full cool-down and readout chain verification (1–2 weeks)

Cool down with the QPU installed. 3–7 days to base temperature depending on cryostat class and payload mass.

Once at base temperature, verify the readout chain. Wide-sweep resonator spectroscopy identifies all readout resonator frequencies and measures internal quality factor (Q_i, target above 10⁴) and coupling quality factor (Q_c). Compare the measured frequencies against the vendor-supplied frequency list. Optimize the TWPA: sweep pump power and frequency to maximize signal-to-noise ratio on the resonator peaks, targeting over 15 dB gain across 4–8 GHz with gain flatness below 3 dB. Verify dispersive readout: with approximately 1,000 shots per qubit, confirm visible separation of ground-state and excited-state blobs in the IQ plane.

Phase 5: Single-qubit characterization and calibration (days to weeks)

This is where calibration software (Q-CTRL Boulder Opal Scale-Up, QuantrolOx Quantum EDGE, or QM QUAlibrate) earns its license fee. The following sequence applies to each qubit individually:

Qubit spectroscopy (two-tone): Identify the ground-to-first-excited-state transition frequency for each qubit. Compare against vendor specifications (within ±50 MHz). For tunable qubits, sweep flux bias to map the frequency-vs-flux curve and identify the sweet spot.

Rabi oscillations: Sweep drive amplitude (power Rabi) and duration (time Rabi) to calibrate the π and π/2 pulse amplitudes and durations. Typical π pulse: 20–50 ns Gaussian or DRAG envelope.

T1 measurement: Exponential decay of the excited-state population. Target: T1 at or above 40 µs (QuantWare Gen-D specification), ideally above 100 µs. This is the first real test of whether your cryogenic environment supports the QPU’s potential. If T1 is significantly below the vendor datasheet, check IR filter integrity, magnetic shielding seating, and MXC attenuator thermalization.

T2-Ramsey and T2-echo: Phase coherence measurements. T2-Ramsey reveals the dephasing rate (typically T1/2 to T1). T2-echo (Hahn echo) refocuses low-frequency noise. Target: T2-echo at or above 30 µs.

DRAG calibration: Sweep the DRAG coefficient to minimize leakage from the computational subspace to the second excited state. Verify with the AllXY sequence (21 gate pairs; all points should fall within ±2% of ideal).

Single-qubit randomized benchmarking (RB): 30–50 sequence lengths × 50 random sequences × 100 shots. This measures average single-qubit gate fidelity. Target: at or above 99.9%.

With automated calibration, single-qubit characterization for a 20-qubit chip takes 1–3 days. Without automation, expect 2–4 weeks.

Phase 6: Two-qubit calibration (weeks)

This phase dominates the timeline for systems above 10 qubits. A 20-qubit chip with nearest-neighbor connectivity has approximately 24 qubit pairs; a 64-qubit chip can have 90+.

For each pair, the sequence runs: coupler characterization (sweep coupler flux, identify on/off coupling ratios, verify residual ZZ coupling below 50 kHz in the off state), two-qubit gate calibration (sweep gate parameters for CZ or iSWAP, target conditional phase = π for CZ with leakage below 0.5%), ZZ cancellation (tune cancellation tone amplitude and frequency to push residual ZZ during idle below 10 kHz), and two-qubit interleaved randomized benchmarking (target: two-qubit fidelity at or above 99.5%).

The IQM/LRZ paper reports approximately 4 weeks of on-site physical installation plus 3 weeks of remote commissioning for their 20-qubit system. Q-CTRL reports that automated cold-start tune-up with Boulder Opal Scale-Up achieves full bring-up from cool-down to certified system in less than a day for a 5-qubit chip and approximately 3 weeks for a 20-qubit system. The QuantrolOx Quantum EDGE platform achieved fully automated two-qubit gate creation in under 25 minutes per pair (compared to approximately one week manually).

Phase 7: System-level benchmarking and SLA acceptance (1–2 weeks)

Quantum volume measurement (target: QV at or above 2^n where n is the number of qubits for which >2/3 of heavy outputs are achieved). CLOPS (circuit-layer operations per second) to quantify sustained throughput. Cross-talk mapping via simultaneous randomized benchmarking on all qubit pairs, to identify problematic crosstalk pairs for mitigation. Readout assignment error matrix (1,000 shots per basis state preparation; per-qubit readout fidelity at or above 97.5%). Drift characterization: repeat T1, T2, and single-qubit RB every hour for 24 hours to establish the recalibration cadence.

The IQM/LRZ team reports a quick recalibration cycle of approximately 40 minutes and a full recalibration cycle of approximately 100 minutes. Systems can run 100+ days unattended between major recalibrations once tuned, with automated frequency, amplitude, and DRAG recalibration running every 1–6 hours.

Keeping it running: operations and maintenance

Commissioning a superconducting quantum computer is a milestone. Keeping it running at certified fidelity is a continuous operation.

Monitoring. Cryostat temperatures at every stage (50 K, 4 K, still, cold plate, MXC) logged every 1–10 seconds. Pulse-tube head pressure and motor current. Gas-handling system mixture composition. Turbo-pump speed and vacuum (target below 1×10⁻⁵ mbar). Compressor health. UPS state. Control-rack inlet temperatures. Qubit metrics: T1, T2, and gate fidelity sampled hourly; readout fidelity per shot. Integrate into standard HPC monitoring (Grafana, Prometheus) using the cryostat vendor’s API (Bluefors Gen-2 control software, Maybell data viewer) and qubit dashboards from Q-CTRL or QuantrolOx.

Preventive maintenance calendar. Pulse-tube cold-head service every 18–24 months (rotary valve and motor replacement). Compressor adsorber replacement annually. Helium-3 mixture check annually. Gas-handling system filter replacement every 12 months. UPS battery test biannually. Helium recovery system quarterly inspection. Plan at least one planned warm-up and service window per year: budget 5–10 days of total downtime (warm-up, service, cool-down, recalibration).

QPU replacement. Swapping a QPU requires a full warm-up. Budget the same 5–10 day window. Always re-characterize the entire cryogenic chain after any internal change. QuantWare’s product line offers a documented upgrade path: Soprano-D5 to Contralto-D21 to Tenor-D64, on the same form factor, so a QPU upgrade can reuse the existing cryostat and most of the wiring.

The unplanned warm-up. The costliest operational event. A power outage that drops the pulse tube, a compressor failure, or a cooling-water interruption can warm the MXC above 1 K. If that happens: recover the helium-3 (do not vent it; it costs $2,500/liter), diagnose the root cause, repair, cool back down, and run the full recalibration sequence. Minimum 5–10 days. This is why the playbook insists on: online double-conversion UPS (20-minute ride-through minimum), dedicated chilled-water loop with redundancy, closed-loop gas handling, and at least one spare helium-3 charge on site.

Personnel. A production QOA superconducting system requires: 1 facility/cryogenic engineer (pulse-tube service, vacuum, gas handling, He-3 management), 1–2 quantum control specialists (RF engineering, calibration, pulse optimization), 1 HPC/DevOps engineer (NVQLink, Slurm, authentication, API surface), 1–2 software engineers (Qiskit/CUDA-Q framework integration), and 1 site-reliability engineer rotation (monitoring, on-call, incident response). For a single-cryostat research lab, 3–5 FTEs can operate the system. For a production service with external users, plan 5–8 FTEs plus vendor support contracts.

What goes wrong and how to fix it

A calibration sequence that reports “all qubits below threshold” is the beginning, not the end. Here is what the playbook’s troubleshooting catalog documents from field deployments.

T1 below vendor spec after transfer. The most common integration surprise. The QPU was characterized in the vendor’s cryostat with their wiring and shielding. Your installation has different thermal loads, potentially different IR filter performance, and different magnetic environments. Diagnostics: compare T1 at different MXC temperatures; check whether T1 improves after 24 hours at base temperature (quasiparticle settling). Fixes: add or verify eccosorb IR filters at cold plate and MXC, verify mu-metal and Nb shield seating, confirm MXC attenuator thermal contact with the plate.

Intermittent qubit frequency jumps. Two-level-system (TLS) defects in the substrate or junction barrier couple to the qubit and cause discrete frequency shifts lasting minutes to hours. There is no fast fix; operate at a slightly different frequency to detune from the defect, or wait for the TLS to shift away. Cosmic-ray impacts can also cause correlated frequency jumps across multiple qubits; surface-code QEC handles these statistically. QuantWare’s VIO 3D-wiring architecture is designed in part to reduce TLS density.

No readout resonator peaks visible. Check that the TWPA pump tone is on (verify pump source power and frequency at the room-temperature end). If the pump is confirmed, sweep a broader frequency range on the VNA. If still no signal, run TDR on the readout line to check for a broken connection. The most common failure point is a connector at the top plate that was not properly torqued during wiring installation.

MXC temperature stuck above 20 mK. Check still temperature (should be ~700 mK; if high, the dilution circuit may be blocked). Check mixture composition on the gas-handling system (helium-3/helium-4 ratio may have drifted). Listen for unusual compressor sounds (mechanical issues). If the mixture is contaminated: warm up, recover gas, replace mixture, re-charge. If the pulse tube has degraded: schedule cold-head service.

Two-qubit fidelity low despite good single-qubit numbers. Measure leakage to the second excited state (leakage benchmarking). Measure ZZ coupling via Ramsey with the neighbor qubit excited versus ground. Check the coupler operating point. If ZZ is too high, recalibrate the coupler flux; if leakage is the bottleneck, add DRAG leakage suppression or increase the gate duration slightly.

What “good” looks like in 2026

Performance targets for a superconducting QPU deployed in a QOA build:

T1 at or above 40 µs, with best-in-class labs now operating above 100 µs on individual qubits. T2-echo at or above 30 µs. Single-qubit gate fidelity at or above 99.9%. Two-qubit gate fidelity at or above 99.5% (references: Google Willow 99.67% CZ; Rigetti Ankaa-3 99.0% median iSWAP, 99.5% median fSim). Single-shot readout fidelity at or above 97.5%. Surface-code cycle time at or below 1.5 µs (Google Willow: 1.1 µs). System uptime above 95% steady state, excluding planned maintenance. Recovery time after unplanned warm event: 5–10 days minimum.

These numbers will improve. The benchmarks that would change procurement recommendations: a verified 99.99% two-qubit gate fidelity on a QOA-compatible processor, or Riverlane Deltaflow demonstrating MegaQuOp (10⁶ error-corrected operations) before the end of 2026. The first would accelerate the timeline for production-grade QEC. The second would trigger the first real fault-tolerance procurement wave.

For the cost implications of building at each tier, from a $1.96M entry system to a $30M+ industrial installation, see the dedicated cost and procurement article in this series. For the NVQLink, QRMI, and software stack integration that connects your superconducting system to HPC resources, see the HPC integration guide. For how the integration challenge differs for other modalities, see the trapped-ion, neutral-atom, photonic, and silicon-spin build guides in this series.

The superconducting QOA build is the most documented, most repeated, and most supported pathway to assembling a quantum computer from vendor components. Q-PAC proved it can be done in five months. The engineering is real, the components are available, and the integration discipline is established. What remains is execution.