You Can Now Build a Quantum Computer from Off-the-Shelf Components

Introduction

On 16 March 2026, a consortium led by Elevate Quantum announced that Q-PAC (the Quantum Platform for the Advancement of Commercialization) was operational at the Quantum Commons campus in Denver, Colorado. The system uses a QuantWare QPU, Qblox control electronics, a Maybell Quantum cryostat, and Q-CTRL calibration software. Five different companies supplied five different layers of the stack. An integration team assembled them into a working quantum computer. The whole process, from concept to cloud-accessible operation, took five months.

Five months. That timeline matters more than the qubit count.

A year earlier, in May 2025, the Dutch quantum ecosystem put Tuna-5 online through the Quantum Inspire cloud. This five-qubit transmon system was built under the HectoQubit/2 project by QuTech, QuantWare, Qblox, Orange Quantum Systems, and Delft Circuits. A 100-qubit successor, integrating Delft Circuits’ Cri/oFlex cabling, is targeting September 2026 as part of the EU Quantum Flagship’s OpenSuperQPlus project.

In Munich, the IQM/LRZ Q-Exa system has been integrated into the Leibniz Supercomputing Centre’s HPC environment since September 2025, with 250 days of calibration telemetry published in arXiv:2509.12949. Euro-Q-Exa, the EuroHPC follow-on, inaugurated in February 2026 with 54 superconducting qubits on IQM’s Radiance platform and a 150-qubit upgrade planned by the end of this year. The total acquisition cost: €25 million, co-funded by the EuroHPC Joint Undertaking and the German federal and Bavarian state governments.

And in Naples, QuantWare’s Tenor-D64 QPU powers Italy’s largest quantum computer at the University of Naples Federico II, a deployment recognized with the 2026 Gold Edison Award in High-Density Computing Infrastructure.

These are not lab prototypes or press-release vapor. They are production systems running operational workloads, built from components sourced from different vendors in different countries. Q-PAC uses a Dutch QPU, Dutch control electronics, an American cryostat, and Australian calibration software. The supply chain spans three continents. The integration happened in Colorado.

This is the Quantum Open Architecture model operating at commercial scale. And it changes the calculus for anyone considering quantum computing procurement.

What this series covers

This Deep Dive series is the practical engineering companion to two related series on PostQuantum.com. My What It Takes to Build a Quantum Computer series maps the supply chains: who makes the dilution refrigerators, the laser systems, the control electronics, the cabling, the QPU chips. My Quantum Systems Integration & QOA series covers the architecture philosophy: why the industry is moving from monoliths to modules, and what systems integration means in a quantum context.

This series covers what happens in between: you have the components; now what? What does the facility need to look like? How do you design a signal chain that actually delivers microwave pulses to a chip sitting at 10 millikelvin? What happens during the weeks-long calibration process between “cool-down complete” and “first useful computation”? How much does all of this cost, and who pays?

Each article in the series tackles a different dimension of the problem:

A dedicated facility preparation guide covers the site requirements that most data centers cannot meet: floor loading, vibration isolation, EMI shielding, power conditioning, chilled water, and helium storage. Individual build guides for each major qubit modality — superconducting, trapped-ion, neutral-atom, photonic, and silicon-spin — explore the specific integration challenges, facility requirements, and timelines for each approach. A dedicated article on cryogenic infrastructure covers the dilution refrigerators, helium-3 supply constraints, and I/O wiring wall that dominate cost and schedule for any superconducting or silicon-spin build. The HPC integration guide covers NVQLink, QRMI, the software stack gap, and the path to real-time QEC decoding. And a procurement-focused piece breaks down total cost of ownership at every scale, from a $1 million educational system to a $500 million national facility.

The analysis draws on Applied Quantum’s Systems Integration Playbook, supplemented by the published deployment data from Q-PAC, IQM/LRZ, and QuTech. Where vendor claims are roadmap items rather than delivered capability, I say so.

The seven layers you are actually buying

When an organization decides to procure an on-premises quantum computer, the procurement decision involves at least seven distinct technology layers. In the monolithic model (IBM, Google, Quantinuum selling you a complete, vertically integrated system), a single vendor controls all seven. In the QOA model, each layer can be sourced independently.

Layer 1: The quantum processing unit (QPU). The chip that holds the qubits. For superconducting systems, this is a transmon circuit fabricated on silicon or sapphire, operating at 10–20 millikelvin. QuantWare is the highest-profile pure-play QPU supplier, with over 50 customers across 20 countries and a product line spanning 5-qubit (Soprano) through 64-qubit (Tenor) processors. Rigetti’s Novera offers a 9-qubit standalone QPU with 4–6 week delivery. For trapped-ion systems, the market is more vertically integrated, though Infineon’s socketed ion-trap-on-carrier (now part of the IonQ pipeline following the $1.075 billion Oxford Ionics acquisition) represents the first component-level offering. For neutral atoms, Pasqal’s Orion series ships as a largely integrated appliance, but one that plugs into standard server racks at room temperature.

Layer 2: Cryogenic infrastructure. The dilution refrigerator that cools the QPU to millikelvin temperatures. This is the most expensive, longest-lead, and physically largest component in a superconducting quantum computer. Bluefors (Finland) dominates the market with over 1,500 systems shipped. Maybell Quantum (Colorado) offers the Big Fridge with integrated vibration isolation and MIT Lincoln Lab’s flex wiring technology. Oxford Instruments (UK) has cut lead times by roughly 50% through a factory-reconfiguration program. For neutral-atom and trapped-ion systems, the core QPU operates at room temperature or moderate cooling; the cryogenic requirement shifts to the detector subsystem or disappears entirely. This distinction changes the procurement equation for facility preparation.

Layer 3: Control electronics. The room-temperature hardware that generates the microwave pulses controlling the qubits and digitizes the readout signals. Three production-grade Western vendors compete: Qblox (Netherlands), Quantum Machines (Israel), and Zurich Instruments (Switzerland, Rohde & Schwarz group). All three are FPGA-based, NVQLink-compatible, and priced in the $200K–$500K range for an entry configuration. For a deep analysis of these platforms and what differentiates them, see my article on quantum control systems.

Layer 4: Cryogenic wiring and the signal chain. Every qubit needs multiple RF and DC control lines connecting room-temperature electronics to the millikelvin processor. Conventional coaxial cables top out at roughly 168 channels per cryostat loader. Delft Circuits’ Cri/oFlex (NbTi superconducting stripline on polyimide, 0.3 mm thick, with integrated attenuators and filters) pushes that to 256 channels per loader today, with a published roadmap to 4,096 by 2029. This is the binding constraint on qubit scaling for superconducting systems, and any integrator starting a new build in 2026 should specify flex cabling from day one. A coax-only design is a future retrofit cost waiting to happen.

Layer 5: Calibration and tuning software. The automated routines that turn a cooled-down chip into a characterized, gate-calibrated quantum processor. Q-CTRL’s Boulder Opal Scale-Up (the engine inside Q-PAC), QuantrolOx’s Quantum EDGE (installed at the UK National Quantum Computing Centre), and Quantum Machines’ QUAlibrate are the three Western platforms. The difference between automated and manual calibration is the difference between a three-week bring-up and a three-month bring-up for a 20-qubit system.

Layer 6: Software framework and middleware. The programming model, job scheduler, and orchestration layer. This is where the Western QOA stack is weakest. There is no single-download quantum operating system equivalent to what Origin Quantum released as Origin Pilot V4.0 in February 2026. Western integrators assemble a stack from Qiskit (IBM), CUDA-Q (NVIDIA), LabOne Q (Zurich), QUA (Quantum Machines), and custom Kubernetes/Slurm orchestration. The Quantum Utility Block (QUB) reference architecture from QuantWare + Q-CTRL + Qblox is the closest thing to a standardized integration recipe.

Layer 7: HPC integration. Connecting the quantum computer to classical compute resources so it functions as a co-schedulable accelerator. NVIDIA’s NVQLink, announced in October 2025 with 17 QPU builders and 9 U.S. national laboratories, provides 400 Gb/s GPU-QPU throughput and measured round-trip latency of 3.96 µs. The Quantum Resource Management Interface (QRMI), demonstrated by Pasqal with NVIDIA CUDA-Q in March 2026, allows QPUs to operate as Slurm-native schedulable resources. NVQLink + CUDA-Q + QRMI is the most documented and widely adopted Western integration path for low-latency QPU-HPC coupling as of May 2026.

In the vertically integrated world, a buyer evaluates one vendor against another. In the QOA world, a buyer (or their integrator) must make independent decisions at each layer, manage multi-vendor interfaces, and accept responsibility for system-level performance that no single vendor guarantees. The integration burden is bounded but real. It requires cryogenic engineering, microwave engineering, RF signal integrity, vacuum science, pulse-level quantum control, calibration science, HPC networking, and information security expertise, all simultaneously.

That is why independent systems integrators exist.

What “open architecture” does and does not mean

I want to be precise about a term that gets used loosely. Quantum Open Architecture is a commercial and engineering movement, not a formal standard. It describes the disaggregation of the quantum computing stack into specialized, interoperable component layers. The term was popularized by QuantWare and adopted by the Dutch quantum ecosystem, the Q-PAC consortium, and the Open Compute Project’s quantum workstream.

QOA does not mean plug-and-play commodity compatibility. Not yet. Cryogenic mechanical interfaces, sample-holder form factors, timing semantics, calibration metadata schemas, and health-monitoring protocols remain largely vendor-defined or project-defined. IEEE has working groups on quantum computing architecture and terminology, and QRMI is emerging as the HPC-facing abstraction, but the physical interfaces between a cryostat’s mixing chamber plate, a QPU sample holder, and a wiring tree still require custom adapter brackets and vendor-specific engineering guidance.

“Open architecture” today means integrable and increasingly modular. It does not mean frictionless commodity plug compatibility. The difference is the difference between building a PC from components in 2024 (standardized everything, takes an afternoon) and building a PC from components in 1982 (you could do it, but you needed to know what you were doing, and half the afternoon was spent resolving bus conflicts). The quantum industry is somewhere around 1985 on this timeline: the components exist, the value proposition is clear, but the integration still requires genuine expertise.

That gap is shrinking. The QUB reference architecture, validated by Q-PAC’s five-month deployment, provides pre-validated procurement blueprints at three tiers: Small (5 qubits), Medium (17–21 qubits), and Large (41+ qubits). Q-PAC’s roadmap explicitly states that the same platform will support 100-qubit-class processors heading into 2027 without replacing infrastructure. That upgrade path (swap the QPU, add control modules, keep the cryostat and facility) is the QOA thesis in action.

The capital markets have voted

QuantWare’s $178 million Series B, announced 5 May 2026, is the largest private round ever raised by a dedicated quantum processor company. Led by Intel Capital and In-Q-Tel, with participation from ETF Partners and existing investors, the capital funds two things: the VIO-40K modular processor architecture targeting 10,000 qubits by 2028, and KiloFab, a dedicated quantum open architecture fabrication facility in Delft that will increase production capacity by 20×.

The investor list tells a strategic story. Intel Capital is the venture arm of the company whose x86 architecture defined the open-standards computing revolution. In-Q-Tel is the U.S. intelligence community’s strategic investment arm. Both chose to bet on the modular QPU supplier model rather than the vertically integrated full-stack model. QuantWare reports having shipped hardware to over 50 customers across 20 countries. As I discussed in my conversation with QuantWare CEO Matt Rijlaarsdam, this mirrors the pattern from classical computing: the component supplier that enables an ecosystem creates more value than the one that locks customers into a proprietary stack.

But the capital investment isn’t only in processors. The full QOA ecosystem is capitalizing in parallel. Bluefors, the dominant cryostat vendor, continues to expand its manufacturing capacity. Qblox and Quantum Machines have both raised significant rounds to scale control electronics production. Delft Circuits is scaling Cri/oFlex manufacturing. The entire supply chain is industrializing simultaneously.

The hard problems are engineering, not physics

The most important thing a potential quantum computer buyer should understand in 2026: the physics works. Superconducting transmon qubits achieve single-qubit gate fidelities above 99.9% and two-qubit gate fidelities above 99.5%. Google’s Willow chip demonstrated below-threshold error suppression at surface code distances 3, 5, and 7. QuEra and Harvard demonstrated 96 verified logical qubits on 448 physical qubits. Quantinuum’s Helios achieved 48 error-corrected logical qubits at a 2:1 physical-to-logical ratio.

The engineering, on the other hand, presents four constraints that will dominate integration decisions for the rest of this decade:

Constraint 1: Helium-3. The working fluid in every dilution refrigerator is derived almost entirely from the radioactive decay of tritium in nuclear weapons stockpiles. Terrestrial supply runs at roughly 22,000–30,000 liters per year. Demand from quantum computing, medical imaging, neutron detection, and fusion research is estimated at 40,000–60,000 liters per year and rising. Market prices range from $1,900 to $2,600 per liter. A Bluefors XLD1000sl holds approximately 40 liters, roughly $100,000 of a working fluid that must be recovered, not vented, after every servicing event. Bluefors and Maybell Quantum have both signed forward-purchase agreements with Interlune for lunar-regolith-extracted helium-3, but Interlune CEO Rob Meyerson has acknowledged that commercial-scale lunar extraction is “going to be in the early 2030s, no earlier than that.” Until then, helium-3 is a structural bottleneck.

Constraint 2: Cryogenic I/O density. Every superconducting qubit requires multiple RF/DC control and readout lines connecting room-temperature electronics to the millikelvin processor. Conventional coaxial cables are too thick, too thermally conductive, and too rigid to support more than a few hundred qubits per cryostat. Delft Circuits’ Cri/oFlex roadmap (256 channels per loader today, 1,024 by 2027, 4,096 by 2029) defines the scaling ceiling. Without this wiring technology or its equivalent, superconducting quantum computers cannot scale past roughly 200 qubits per cryostat regardless of QPU quality.

Constraint 3: Real-time quantum error correction decoding. A surface-code cycle takes about 1 microsecond on superconducting hardware. The decoder must process syndrome data and return corrections within roughly 10 cycles (10 µs) for distance-7 surface code. The NVQLink round-trip of 3.96 µs fits within this budget, making GPU-hosted decoders (Riverlane Deltaflow, NVIDIA AlphaQubit) practical. But this requires a dedicated GPU node connected via NVQLink to the control electronics, running the decoder continuously. Without it, error correction is offline-only, useful for research but not for running error-corrected algorithms. Any system designed for 2027+ should be QEC-ready, which means NVQLink-compatible control electronics and a decoder path specified from day one.

Constraint 4: Facility requirements. A superconducting quantum computer is not a server rack. A fully loaded cryostat weighs roughly 750 kg concentrated on a small footprint. Standard raised flooring in most data centers is insufficient. Floor loading must support at least 1,000 kg/m². Vibration targets require a minimum 100-meter exclusion zone from elevator shafts, train lines, and freight docks. EMI shielding demands DC magnetic fields below 100 µT and AC fields below 1 µT near the cryostat. Standard fluorescent lighting generates unacceptable interference. Chilled water at 15–25°C (substantially colder than the ~45°C warm-water loops in modern energy-efficient HPC liquid-cooling) feeds the pulse-tube compressors. A grid loss that takes the pulse tube down can cost 5–10 days of recovery if the cryostat warms above 1 K. The Open Compute Project launched its quantum infrastructure workstream in late 2025 to standardize these facility parameters, but most existing data centers will require significant remediation.

These constraints apply primarily to superconducting and silicon-spin systems. Neutral-atom quantum computers (Pasqal’s Orion series runs in a standard server rack at room temperature with 3 kW power draw) sidestep the entire cryogenic infrastructure stack. This modality-specific contrast is one of the things that makes the “how to build” question fundamentally different depending on which type of quantum computer you’re building.

How integration actually works: the superconducting reference

The Q-PAC five-month timeline provides the reference deployment for superconducting QOA integration. The sequence, synthesized from the Q-PAC deployment data and Applied Quantum’s playbook, runs roughly as follows:

Months 1–2: Site preparation and procurement, in parallel. Vibration survey (25+ hours of accelerometer data), EMI spectrum analysis (4–8 GHz), magnetic field mapping, power quality analysis. Floor remediation if needed. Vibration isolation pad, EMI shielding, 3-phase 63A power panel, online double-conversion UPS, chilled-water plant, helium recovery system. Simultaneously: cryostat order placed (longest lead item at roughly 4 months for a preconfigured Bluefors system, 6 months for Maybell Big Fridge), QPU order, control electronics order (confirm FPGA allocation), wiring order, calibration software license.

Months 3–5: Integration and bring-up. Cryostat arrives, vendor field-service installs it (roughly 1–2 weeks). First empty cool-down to base temperature (24–72 hours for an LD/XLD-class, 3–7 days fully loaded). Wiring tree installation with attenuators, filters, isolators, TWPAs, HEMT amplifier, and magnetic shielding (1–3 weeks plus a verification cool-down/warm-up cycle). QPU installation on the mixing chamber. Full cool-down with QPU. Then the calibration sequence: resonator spectroscopy, qubit spectroscopy, Rabi oscillations, T1/T2 measurements, single-qubit gate calibration, two-qubit gate calibration, readout optimization, system-level benchmarking with quantum volume, CLOPS, and cross-talk mapping. With automation (Q-CTRL Boulder Opal Scale-Up), full bring-up from first cool-down takes less than a day for a 5-qubit chip and approximately 3 weeks for a 20-qubit system. Without automation, a 20-qubit bring-up can take months.

Month 6 onward: Operations handover. Monitoring dashboards configured, automated recalibration deployed, user API and authentication set up, ongoing support contract activated.

The IQM/LRZ paper arXiv:2509.12949, covering 250 days of operational data from a 20-qubit system in a production HPC environment, provides independent confirmation of these timelines. The LRZ team reports roughly 4 weeks of on-site physical installation plus 3 weeks of remote commissioning, a quick recalibration cycle of approximately 40 minutes, and a full recalibration cycle of about 100 minutes. Systems can run 100+ days unattended between major recalibrations once tuned.

The numbers that matter for evaluating a superconducting QPU in 2026: T1 (energy relaxation time) at or above 40 µs, ideally above 100 µs. T2-echo (phase coherence) at or above 30 µs. Single-qubit gate fidelity at or above 99.9%. Two-qubit gate fidelity at or above 99.5% (Google Willow achieved 99.67% CZ; Rigetti Ankaa-3 reported 99.0% median iSWAP). Single-shot readout fidelity at or above 97.5%. Surface-code cycle time at or below 1.5 µs (Google Willow: 1.1 µs). If your vendor-supplied QPU does not meet these thresholds on your cryostat, the first diagnostic steps are checking infrared filter integrity (quasiparticle poisoning is the most common T1 killer), verifying mu-metal and niobium magnetic shields are properly seated, and confirming that the mixing chamber attenuator is thermalized rather than floating.

These specifics matter because vendor-typical performance figures are not guaranteed minimums. QuantWare’s published 99.9% single-qubit fidelity and 99.7% two-qubit fidelity are device-typical results for the Gen-D product line. Vendors do not publish per-chip guaranteed minimums. Measure your own chip. The IQM/LRZ calibration telemetry shows performance variation across qubits on the same chip and drift over time. Automated recalibration every few hours is not optional, it is mandatory for any production deployment.

For the detailed signal chain engineering, the calibration state machine, and the component-level bill of materials, see the dedicated superconducting build guide in this series.

What goes wrong

Integration articles that describe only the happy path are not useful. Here is what actually fails during quantum computer builds, drawn from the playbook’s troubleshooting catalog and the IQM/LRZ operational data.

The most common surprise for first-time operators: T1 values significantly below vendor specifications after installation. The QPU was characterized by the vendor in their cryostat. When you install it in your cryostat, with your wiring tree, your attenuator chain, and your magnetic shielding, performance can degrade. The usual suspects are infrared photon leaks causing quasiparticle poisoning (fix: add or verify eccosorb IR filters at the cold plate and mixing chamber stages), insufficient magnetic shielding (fix: verify the mu-metal and superconducting niobium shields are properly seated around the sample holder), and poor thermalization of the final-stage attenuator (fix: confirm thermal contact between the attenuator and the mixing chamber plate). The diagnostic is straightforward: if T1 improves after the chip has been sitting at base temperature for 24 hours, quasiparticle settling is likely the explanation.

Readout fidelity below 95% usually traces to insufficient TWPA gain (re-optimize the pump tone frequency and power), poor IQ-plane discrimination (optimize readout pulse amplitude and integration time), or thermal population of the excited state (check that the mixing chamber is actually below 15 mK with the full wiring load installed).

Two-qubit gate fidelity lagging despite good single-qubit performance typically means leakage to the second excited state (add DRAG leakage suppression), residual ZZ coupling between neighboring qubits is too high (recalibrate the coupler flux bias), or thermal population is contaminating the initial state.

And the failure that costs the most time: an unplanned cryostat warm-up from a power outage, compressor failure, or coolant water interruption. If the mixing chamber exceeds 1 K, budget a minimum of 5–10 days for recovery: warm-up, diagnosis, potential helium-3 recovery, cool-down, full recalibration. This is why the playbook specifies an online double-conversion UPS sized for at least 20 minutes of full load as non-negotiable infrastructure. The UPS doesn’t need to power the system indefinitely; it needs to ride out grid sags and provide enough time for a controlled warm shutdown that protects the helium-3 mixture.

Each modality presents a different integration challenge

The superconducting reference above covers the most mature QOA pathway. But the integration challenge looks fundamentally different depending on which qubit modality you choose. The subsequent articles in this series cover each in detail; here is the high-level contrast.

Superconducting transmon is the most developed QOA supply chain. Integration is dominated by cryogenic infrastructure: dilution refrigerators, helium-3 management, the I/O wiring wall, and precision microwave signal chains with 60+ dB of carefully staged attenuation across five thermal stages. The QPU itself is the simplest component to procure. QuantWare ships characterized chips with pre-delivery T1, T2, and frequency data. The facility requirements are extreme (EMI shielding, vibration isolation, dedicated chilled-water loops), and the operational overhead includes annual pulse-tube service, helium-3 recovery after every warm-up, and continuous calibration drift monitoring. Timeline from empty lab to first qubit signal: 5–9 months.

Trapped-ion shifts the integration burden from cryogenics to optics and ultra-high vacuum. The core QPU operates at room temperature (or moderate cooling). The dominant procurement challenge is the laser subsystem: 5–10 lasers per ion species, each requiring sub-megahertz linewidth and tight intensity stabilization via cavity-locked external-cavity diode lasers or frequency combs. For barium ions (Quantinuum, IonQ Tempo), the laser requirements are particularly demanding. Ultra-high vacuum chambers at 10⁻¹¹ mbar require days-to-weeks bake-out at ~200°C, and a single vacuum leak means starting the bake-out over. The optical table footprint is typically 1.5 × 3 meters with Class 1000 cleanliness requirements. The QCCD architecture (quantum charge-coupled device), demonstrated commercially by Quantinuum’s Helios with the industry’s first 2D-routable junction-based ion transport, adds ion shuttling between functional zones for storage, gate operations, and readout. Independent integrator assembly of trapped-ion systems is less mature than superconducting (most systems ship as vertically integrated appliances), but the Infineon socketed ion-trap-on-carrier signals the direction of the supply chain.

Neutral-atom is the easiest modality for an enterprise to deploy on-premises from a facility perspective. No cryogenics for the core processor. Pasqal’s Orion fits in a standard server rack, draws 3 kW, and runs at room temperature. The facility preparation delta compared to superconducting is dramatic: no 1,000 kg/m² floor loading, no chilled-water plant, no helium recovery, no pulse-tube compressors generating 85+ dB noise. The integration challenge moves to the laser and optics subsystem: trap lasers (typically 1064 nm at ~10 W) with spatial light modulators or acousto-optic deflectors for tweezer array generation, Rydberg excitation lasers (UV or two-photon path at ~420 nm + ~1013 nm, sourced from Toptica or M-Squared Lasers), and EMCCD/sCMOS cameras for fluorescence imaging. Atom loading requires a magneto-optical trap (MOT) for initial cooling and an ultra-high vacuum chamber, but these are smaller and simpler than trapped-ion equivalents. The Pasqal QRMI demonstration with NVIDIA CUDA-Q in March 2026 makes neutral atom the first modality with a production-validated HPC integration path. Pasqal has delivered systems to GENCI France, Jülich, CINECA Italy, and OVHcloud, each integrated into existing data-center environments without the cryogenic facility remediation that superconducting would have required.

Photonic is the vertically integrated exception. PsiQuantum fabricates its Omega chipset at GlobalFoundries. Xanadu fabricates at its own facility. Independent integrator assembly of a photonic quantum computer from components is not yet commercially practical. The core processor operates at room temperature (a significant advantage), but the detector subsystem (superconducting nanowire single-photon detectors, or SNSPDs) requires cryogenic cooling to 0.8–4 K, a qualitatively different infrastructure requirement than superconducting qubits. An integrator’s role today is limited to SNSPD cryogenics, classical networking, and HPC integration around a vendor-supplied photonic system.

Silicon-spin represents the CMOS fabrication thesis: qubits manufactured on the same 300 mm semiconductor lines that produce classical processors. Diraq and imec’s September 2025 Nature paper validated the industrial-fab path with >99% two-qubit gate fidelity across randomly selected wafer devices. The higher operating temperature (approximately 1 K versus 10–20 mK for transmon) enables the use of helium-4-only cryostats, eliminating helium-3 dependency entirely. The supply chain is younger than superconducting, but the long-term cost-per-qubit advantage of CMOS fabrication is compelling. SemiQon ships 4-qubit silicon spin arrays today; Intel distributes Tunnel Falls 12-qubit chips to academic partners.

The common thread across all five modalities: the QPU is rarely the hardest part to procure. The infrastructure around it (the cryogenics, the optics, the signal chain, the calibration, the HPC integration) is where integration expertise creates or destroys value.

What this means for your procurement decision

If you are a CTO, VP of Research, or laboratory director evaluating on-premises quantum hardware in 2026, three conclusions follow from the QOA model’s maturation.

First, you no longer need to commit to a single vertically integrated vendor. The QOA supply chain for superconducting systems is production-validated. You can specify each layer independently, select best-of-breed components, retain upgrade optionality, and engage an independent integrator to manage the multi-vendor build. QuantWare offers a documented upgrade path from Soprano-D5 (5 qubits, ~€60K) through Contralto-D21 (21 qubits, ~€300K) to Tenor-D64 (64 qubits) on the same form factor. Control electronics are modular: add Qblox modules to the same Cluster mainframe. The upgrade path is real and has been demonstrated.

Second, you should build the lab for the next system, not the current one. Three-meter ceiling height. At least 50 kW of 3-phase power capacity. Room for a second rack row. Water loop for a second pulse-tube compressor. Helium recovery infrastructure from day one. The incremental cost of over-specifying the facility is small compared to the cost of a facility retrofit two years later when you upgrade from 20 to 100 qubits.

Third, your threshold for buying hardware has dropped, but it hasn’t disappeared. On-premises quantum hardware makes sense when your workload exceeds 10⁶ shots per month sustained, or when classified or regulated data prohibits cloud transit, or when you have a strategic imperative (sovereignty, talent attraction, sector leadership) that justifies $3–15 million in capital expenditure. If none of those conditions apply, start with cloud access on IBM Quantum, AWS Braket (QuEra, IonQ, Rigetti), or Azure Quantum (IonQ, Quantinuum, Pasqal).

For a breakdown of capital and operational costs across system tiers, see the dedicated article on what a quantum computer actually costs to build and operate in this series.

The security dimension

There is a connection between building quantum computers and securing against them that is easy to miss if you work on only one side of the equation.

Organizations investing in quantum compute capability have a sharper understanding of the threat timeline than anyone else. They know firsthand how quickly gate fidelities are improving, how the resource estimates for breaking RSA-2048 and ECC keep falling, and how the engineering path to a cryptographically relevant quantum computer is plausible within the early 2030s. They also face heightened reputational risk: an organization that operates quantum computers while leaving its own classical infrastructure vulnerable to quantum attack invites scrutiny that no CISO wants to answer.

The PQC migration timeline and the quantum compute build timeline should be coordinated, not siloed. Both have multi-year lead times. Both require board-level investment approval. And the quantum compute team’s knowledge of the threat timeline directly informs the urgency of the CISO’s PQC migration. The PQC Migration Framework at pqcframework.com provides the structured methodology for the security side of this equation. Practical Steps to Quantum Readiness covers the immediate actions.

But the important point for this series is simpler: if your organization is building a quantum computer, your classical API surface should be PQC-migrated from day one. ML-KEM (FIPS 203) for key exchange, ML-DSA (FIPS 204) for authentication, and HNDL risk assessment for any data transiting between your quantum service and your users. The deadlines are already set by regulators, insurers, and clients — regardless of when Q-Day actually arrives.

Where this series goes from here

The nine articles that follow this capstone each go deeper on one dimension of the “how to build” question. They are designed to be read in any order, depending on which modality or constraint matters most to your situation:

The facility preparation guide covers the site requirements that most data centers cannot meet, from vibration isolation to helium storage, with a reference floor plan. The superconducting build guide covers the full integration sequence from empty lab to first qubit signal, with the signal chain engineering, calibration state machine, and component-level specifics that the Q-PAC deployment validated. The trapped-ion build guide covers the shift from cryogenic to optical and vacuum engineering. The neutral-atom build guide covers the room-temperature advantage and what it means for data-center-native deployment. The photonic build guide covers why this modality remains a vertically integrated exception. The silicon-spin build guide covers the CMOS fabrication thesis and the helium-3-free cryogenic pathway. The cryogenic infrastructure article is the piece that makes readers realize a quantum computer is an industrial installation, not a server rack. The HPC integration guide covers NVQLink, QRMI, the Western software stack gap, and the path to real-time quantum error correction decoding. And the cost and procurement article provides the TCO models and funding sources that CFOs and grant writers need.

Each article references Applied Quantum’s Systems Integration Playbook for component-level specifications and integration procedures, supplemented by the latest vendor data and published deployment reports.

The quantum computer that matters isn’t the one with the most qubits. It’s the one that runs, reliably, doing useful work, in your facility, under your control. Getting there is an engineering project, not a physics experiment. This series is the field guide for that project.