Quantum Computing Modalities: Silicon-Spin

(For other quantum computing modalities and architectures, see Taxonomy of Quantum Computing: Modalities & Architectures)

What It Is

Silicon spin qubits encode quantum information in the spin of individual electrons or holes confined in nanoscale semiconductor structures on silicon chips. The qubit states |0⟩ and |1⟩ correspond to spin-up and spin-down in an applied magnetic field. The structures that confine these spins, quantum dots defined by gate electrodes on isotopically purified ²⁸Si substrates, are fabricated using the same lithographic processes that produce every classical processor and memory chip on Earth.

That last detail is the entire thesis of this modality. If quantum dots can function as reliable qubits, then the semiconductor industry’s $700 billion annual investment in 300 mm fabrication lines, photolithography, and process engineering becomes the manufacturing backbone for quantum computing. The cost-per-qubit could eventually follow the same downward trajectory that took classical transistors from dollars per unit to fractions of a cent.

In September 2025, Diraq and imec validated this thesis experimentally. They demonstrated >99% two-qubit gate fidelity on devices fabricated using imec’s standard spin-qubit process flow on an industrial 300 mm wafer, published in Nature. The devices were processed alongside conventional semiconductor production, not cherry-picked hero devices in a university lab. It was foundry-quality silicon, processed at imec (the world’s leading semiconductor R&D center), yielding qubits with error rates at the threshold for quantum error correction. In March 2026, the first universal logical operations on silicon spin qubits were demonstrated. In January 2026, silicon caught its first errors.

From a CRQC standpoint, silicon spin qubits are the long-game contender. They are years behind superconducting and trapped-ion systems in qubit count and QEC demonstrations. But if the CMOS fabrication thesis holds, the scaling trajectory could eventually outpace any modality that relies on specialized, non-semiconductor manufacturing. That “if” is the central question for the decade ahead.

How It Works

Quantum Dot Spin Qubits

The dominant approach. Gate electrodes patterned on a silicon substrate (either a Si/SiO₂ MOS structure or a Si/SiGe heterostructure) create electrostatic potential wells that confine individual electrons. By tuning gate voltages with millivolt precision, each quantum dot isolates exactly one electron. That electron has spin-1/2. Under an external magnetic field (~0.5–1.5 Tesla), the spin-up and spin-down states split by the Zeeman effect, typically by 10–30 GHz. These two states form the qubit.

Single-qubit gates are performed by electron spin resonance (ESR): applying a resonant microwave or RF field that rotates the spin. In practice, most silicon spin systems use electric-dipole spin resonance (EDSR), which exploits either a micromagnet (a cobalt strip near the dot that creates a local magnetic field gradient) or intrinsic spin-orbit coupling to convert an oscillating electric field into an effective magnetic field rotation. EDSR is more practical than global ESR because it can be driven by voltage pulses on nearby electrodes, enabling individual qubit addressing.

Two-qubit gates exploit the exchange interaction. When the barrier between two adjacent quantum dots is lowered (by adjusting a gate voltage), the electron wavefunctions overlap and their spins couple via the Heisenberg exchange Hamiltonian H = J·S₁·S₂. The coupling strength J is exponentially sensitive to the barrier height, which means it can be switched on and off in nanoseconds by small voltage changes. Holding the exchange coupling on for a calibrated duration implements a √SWAP or controlled-phase gate. Gate times are 10–200 ns, comparable to superconducting two-qubit gates.

Two control paradigms compete. In detuning-controlled exchange, the energy offset between neighboring dots is tilted so that one dot’s electron tunnels partially into the neighbor’s potential well, creating exchange coupling. This was the original approach and is simpler to implement but makes the coupling sensitive to charge noise (any fluctuation in the electrostatic environment shifts the detuning, causing gate errors). In barrier-controlled exchange, a dedicated barrier gate between the dots directly modulates the tunnel coupling without detuning the dots’ energies. This decouples the exchange interaction from charge noise at the “symmetric operating point,” where the qubit frequency is first-order insensitive to detuning fluctuations. Barrier-controlled exchange has become the preferred approach in recent high-fidelity demonstrations, including the Diraq/imec >99% result.

Noise Sources and Crosstalk

Three noise mechanisms dominate silicon spin qubit performance:

Charge noise. Fluctuations in the local electrostatic environment, from trapped charges in the oxide, interface defects, or gate voltage noise, shift the quantum dot’s energy levels. Because the exchange coupling J depends exponentially on detuning, charge noise translates directly into gate-frequency fluctuations and two-qubit gate errors. Typical charge noise levels are 1–10 µeV/√Hz. Operating at the symmetric point (barrier-controlled exchange) provides first-order protection, but second-order sensitivity remains. Improving charge noise requires cleaner interfaces, better oxide quality, and more stable gate voltage sources.

Magnetic noise. Fluctuating magnetic fields from residual ²⁹Si nuclear spins (if isotopic purification is imperfect), from nearby micromagnets, or from paramagnetic surface impurities cause dephasing of the electron spin. In isotopically enriched ²⁸Si, this noise source is suppressed by 100–1,000× compared to natural silicon or GaAs, which is why isotopic purification was such a transformative advance. Residual magnetic noise from the micromagnet (used for EDSR) or from surface paramagnets remains a limiting factor for T₂* in some device architectures.

Crosstalk. In a dense array of quantum dots, adjusting one gate electrode affects neighboring dots’ potentials through capacitive coupling. This crosstalk means that tuning qubit 5 can detune qubits 4 and 6. As arrays grow beyond 6–10 qubits, the crosstalk calibration matrix becomes large and interdependent. Automated cross-talk compensation algorithms (analogous to the automated calibration loops used in superconducting systems) are essential for scaling. The Nature Reviews CMOS-spin compatibility assessment identifies crosstalk management as one of the key engineering challenges for the 50–100 qubit regime.

Readout uses spin-to-charge conversion. The spin state is mapped to a charge state that can be detected by a nearby charge sensor (a single-electron transistor or quantum point contact). One common method: Elzerman readout, where the dot’s energy is tuned so that only spin-up electrons can tunnel out to a reservoir, producing a measurable current pulse. RF reflectometry (probing the impedance of the charge sensor at ~100–300 MHz) can speed this up to microsecond-scale readout. Readout fidelity is typically 95–99%, improving with RF reflectometry optimization.

Donor Spin Qubits

An alternative approach uses dopant atoms, typically phosphorus (³¹P), embedded in isotopically purified ²⁸Si. Each phosphorus atom has one extra electron compared to silicon, loosely bound like a hydrogen atom within the crystal. At cryogenic temperatures, this electron is localized on the donor. Both the electron spin and the phosphorus nuclear spin can serve as qubits.

Nuclear spin qubits offer extraordinary coherence: in isotopically pure ²⁸Si, a ³¹P nuclear spin can maintain quantum information for seconds to minutes, because the nucleus is shielded from electrical noise by the surrounding electron cloud. The electron spin provides a fast interface for readout and two-qubit coupling (via exchange with neighboring donors), while the nuclear spin functions as a long-lived quantum memory.

Silicon Quantum Computing (SQC, Australia, led by Michelle Simmons) uses scanning tunneling microscope (STM) lithography to place individual phosphorus atoms with atomic precision, achieving sub-nanometer donor positioning. SQC’s results are covered in the vendor section below.

Hole Spin Qubits

A more recent variant uses holes (missing electrons) rather than electrons as the spin carrier. Holes in silicon or germanium have strong spin-orbit coupling, which means their spin can be manipulated purely electrically, without micromagnets or ESR lines. A fast voltage pulse on a gate electrode directly rotates a hole spin. This could simplify the control infrastructure significantly. Hole-spin qubits demonstrated in silicon FinFETs (May 2024) showed that standard transistor geometries can host spin qubits, further validating the CMOS compatibility thesis.

The Isotopic Purity Advantage

Natural silicon contains 4.7% ²⁹Si, an isotope with a nuclear spin that creates a fluctuating magnetic environment and rapidly dephases electron spins. Isotopically enriched ²⁸Si (with >99.99% purity) eliminates these nuclear spins, extending electron spin coherence times from microseconds to milliseconds and nuclear spin coherence to minutes. SOITEC is the primary supplier of enriched ²⁸Si wafers for the quantum computing industry; imec, GlobalFoundries, and Intel provide fabrication capacity on these substrates.

Operating Temperature

Most silicon spin qubit experiments operate at 10–100 mK in dilution refrigerators, similar to superconducting qubits. But silicon spin has a structural advantage: some demonstrations have shown qubit operation above 1 K, and even at 1.5 K with reduced but still useful fidelity. This is significant because it allows the use of Bluefors XLDHe High Power cryostats that run on helium-4 only, avoiding the helium-3 supply constraint that dominates superconducting system costs. Higher operating temperatures also provide more cooling power for co-located cryo-CMOS control electronics, which is essential for the vision of millions of qubits with integrated control.

Key Academic Papers

Kane (1998). “A silicon-based nuclear spin quantum computer.” The proposal that launched the field: phosphorus donors in silicon as nuclear-spin qubits, coupled via electrode-controlled exchange interaction. Published in Nature.

Loss & DiVincenzo (1998). Proposed using electron spins in semiconductor quantum dots as qubits with exchange-based two-qubit gates. The theoretical blueprint for quantum dot spin qubits. Published in Physical Review A.

Veldhorst et al. / QuTech (2015). First two-qubit gate in silicon: a controlled rotation between two electron spins in a double quantum dot, ~90% fidelity. Published in Nature.

Three labs cross fault-tolerance threshold (January 2022). In a single week, three independent groups (UNSW/Diraq, QuTech/TU Delft, and RIKEN) published silicon spin qubit results exceeding the fault-tolerance threshold (>99% two-qubit fidelity). Published in Nature.

Diraq + imec >99% on 300 mm wafers (September 2025). The paper that validated the industrial-fab thesis. Randomly selected devices from a 300 mm production wafer demonstrated >99% two-qubit gate fidelity, published in Nature (Steinacker et al.). My analysis covers why this result changes the silicon spin outlook.

Silicon runs Grover’s algorithm (February 2025). First real algorithm executed on silicon spin qubits: Grover’s search on four qubits with every gate above fault-tolerance threshold.

First universal logical operations in silicon (March 2026). Demonstrated logical qubit operations on a silicon spin processor, crossing the threshold from physical to logical computation. My analysis.

Silicon catches its first errors (January 2026). First quantum error detection on silicon spin qubits. A necessary precursor to full error correction.

Nature Reviews CMOS-spin compatibility assessment (April 2026). The definitive academic assessment of whether CMOS fabrication processes are compatible with spin qubit requirements. My analysis.

Hole spin qubits in silicon FinFETs (May 2024). Demonstrated that standard FinFET transistor structures can host spin qubits, extending the CMOS compatibility argument to the most advanced transistor architectures.

The Vendor Landscape (May 2026)

Silicon spin is younger commercially than superconducting, trapped-ion, or neutral-atom modalities. No vendor ships a general-purpose silicon spin quantum computer today. But the vendor ecosystem is growing rapidly, and the involvement of semiconductor industry giants (Intel, imec, GlobalFoundries) distinguishes this modality from all others.

Diraq (Australia). The most advanced silicon spin qubit company. Spun out of UNSW (Andrea Morello’s group). Diraq’s Si MOS quantum dot approach uses the 300 mm imec fab for device fabrication, making it the first quantum computing company to demonstrate production-quality qubits on an industrial semiconductor line. The September 2025 Nature paper (>99% two-qubit fidelity on foundry-fabricated devices using imec’s 300 mm process flow) is Diraq’s anchor result. Selected for DARPA QBI Stage B (November 2025). Partnership with Emergence Quantum on millikelvin-CMOS co-integration for control electronics at the qubit stage itself. Received investment from the Australian NRFC in 2025. Diraq’s thesis is that once per-qubit performance crosses the error-correction threshold on industrial wafers, scaling follows from standard semiconductor process engineering.

Intel (USA). The largest semiconductor company actively pursuing silicon spin qubits. Intel’s Tunnel Falls is a 12-qubit silicon spin chip fabricated on Intel’s 300 mm process lines, distributed to academic partners for characterization. Intel has invested in QuantWare‘s Series B round, signaling that it sees silicon spin and superconducting QOA as complementary parts of the quantum ecosystem. Intel’s quantum program is smaller relative to its overall R&D budget than IBM’s or Google’s commitment to superconducting, but its fabrication capability is unmatched.

Intel’s cryo-CMOS control stack is the most developed in the industry and worth understanding in detail, because it addresses the wiring bottleneck that limits every cryogenic quantum computing modality. Horse Ridge II is a 22 nm FinFET system-on-chip that operates at 3 K (the 4 K stage of a cryostat, not the millikelvin stage). It provides 4 RF output channels, each using frequency-division multiplexing to address up to 32 qubits, for a total capacity of 128 qubits from a single chip. Gate fidelity with Horse Ridge II control matches room-temperature baseline at 99.7%. The chip handles qubit manipulation, readout, and multigate pulsing in a single cryogenic package. Pando Tree is Intel’s newer program targeting control electronics at the millikelvin stage itself, co-located directly with the qubits. If Pando Tree succeeds, it eliminates the RF cabling between 3 K and 10 mK entirely, which is the densest and most thermally constrained segment of the wiring tree. The combination of Horse Ridge at 3 K and Pando Tree at mK represents the most complete cryo-CMOS control architecture under development.

SemiQon (Finland, VTT spin-out). Ships 4-qubit silicon spin arrays since March 2024, with a 12-qubit 1D array in development. Uses Si FDSOI (fully depleted silicon-on-insulator) on ²⁸Si substrates. Demonstrated cryo-CMOS transistors with a record 0.3 mV/dec sub-threshold swing at 420 mK. Operates at ~1 K, positioning SemiQon for helium-4-only cryostats. SemiQon is the only vendor currently shipping standalone silicon spin QPU components to external customers, making it the closest analogue to QuantWare in the superconducting QOA market.

Quantum Motion (UK). Si MOS quantum dot qubits using FDSOI technology, targeting CMOS-fab-compatible architectures. Deployed at the UK National Quantum Computing Centre (NQCC). Aims for scalable arrays using standard foundry processes.

Silicon Quantum Computing (SQC, Australia). Founded by Michelle Simmons (2018 Australian of the Year, now running Australia’s National Quantum IC Centre). SQC takes a fundamentally different fabrication approach from every other vendor in this space: scanning tunneling microscope (STM) lithography.

The process works like this: a hydrogen-terminated silicon surface is placed under an STM tip in ultra-high vacuum. The tip selectively removes individual hydrogen atoms from the surface, exposing bare silicon sites. Phosphine gas (PH₃) is introduced, and phosphorus atoms bond only to the depassivated sites, because the surrounding hydrogen mask prevents adsorption elsewhere. The result is atomically precise placement of single phosphorus donors in a silicon lattice, with sub-nanometer accuracy. Subsequent silicon overgrowth buries the donors, and conventional lithography adds gate electrodes for control and readout.

This is the highest-precision qubit fabrication technique in existence. No other approach places individual atoms with comparable accuracy. The tradeoff is throughput: STM lithography is serial (one atom at a time, one tip) and slow compared to photolithographic batch processing. SQC’s path to scaling involves developing parallel multi-tip STM systems and increasing writing speed, but the approach will always produce fewer qubits per unit time than a CMOS fab. In December 2025, SQC demonstrated an 11-qubit, two-register processor linking donor qubits, and in February 2025, silicon ran its first real algorithm: Grover’s search on four qubits with every gate above threshold. SQC’s bet is that atomic-level fabrication precision produces higher-quality qubits than any batch process, and that the quality advantage justifies the throughput cost.

HRL Laboratories (USA). Develops exchange-only silicon spin qubits (using three electrons per qubit, manipulated entirely by exchange interactions without microwave fields). Open-source spinQICK control platform. DARPA-funded.

Equal1 Labs (Ireland). Building a fully integrated silicon quantum processor SoC (system-on-chip), with both qubits and classical control logic on the same die. If viable at scale, this is the most radical implementation of the CMOS integration thesis.

I cover the practical details of assembling a silicon spin quantum computing system in my deep dive on building a silicon-spin quantum computer.

The CMOS Thesis: Promise and Reality

The central argument for silicon spin qubits is that they can ride the semiconductor industry’s existing infrastructure to achieve cost and scale advantages no other modality can match. Here’s the current status as of May 2026:

What has been validated. Diraq and imec proved that 300 mm industrial wafers can produce qubits with >99% two-qubit fidelity using standard spin-qubit process flows. Intel Tunnel Falls demonstrated that a major fab can process 12-qubit quantum chips at volume (24,000 chips per wafer). SemiQon is shipping multi-qubit arrays from a commercial production line. The Nature Reviews CMOS-spin compatibility assessment (April 2026) found no fundamental incompatibility between CMOS processes and spin qubit requirements.

What remains unproven. No one has demonstrated more than ~12 qubits on a single silicon spin chip with full control. The gap between 12 and 1,000 is where the CMOS thesis must deliver: can the same wafer-scale processes that yield billions of uniform transistors yield thousands of uniform qubits? The tolerance for disorder in qubits is much tighter than in classical transistors (a qubit needs its resonance frequency tuned to MHz precision; a transistor just needs to switch on and off). Device-to-device variability in quantum dot charging energies, tunnel couplings, and local magnetic environments remains the primary obstacle to scaling.

The cryo-CMOS connection. The vision of millions of silicon spin qubits depends on co-locating classical control electronics with the qubits inside the cryostat. Intel’s Horse Ridge II and Pando Tree, Diraq’s partnership with Emergence Quantum, SemiQon’s cryo-CMOS transistors, and Equal1’s integrated SoC are all pursuing this. At the current 10–100 mK operating point, each classical transistor in the control circuit dissipates heat that competes with the limited cooling power of the dilution refrigerator. Operating qubits at ~1 K (which some demonstrations support) would provide orders of magnitude more cooling power for co-located electronics, making the cryo-CMOS vision far more tractable.

Comparison to Other Modalities

Silicon Spin vs. Superconducting

Both are solid-state, chip-based, and operate in cryostats. Both use lithographic fabrication. Both have nearest-neighbor connectivity as the default (though superconducting systems can add non-local c-couplers). Gate speeds are comparable (10–200 ns for both). The differences are scale and maturity: superconducting systems have reached 1,121 qubits (IBM Condor) versus ~12 for silicon spin; superconducting QEC has been demonstrated at below-threshold scale (Google Willow), while silicon has just demonstrated first logical operations and error detection.

Silicon spin’s structural advantages: much smaller qubit footprint (~50 nm quantum dot vs. ~200 µm transmon resonator, a 4,000× density advantage in principle), higher operating temperature (~1 K vs. 10 mK), no helium-3 requirement at ~1 K, and the ability to manufacture on existing 300 mm CMOS lines. Superconducting’s advantages: vastly more mature QEC demonstrations, an established QOA component ecosystem, deeper HPC integration (NVQLink), and a two-decade head start in multi-qubit engineering. The competition is between superconducting’s current lead and silicon’s potential for cheaper, denser, more manufacturable qubits in the 2030s.

Silicon Spin vs. Trapped Ion

Very different physical platforms, but a useful comparison on the quality-vs-scale axis. Trapped ions lead in fidelity (99.921% vs. >99% for silicon), connectivity (all-to-all vs. nearest-neighbor), coherence (minutes vs. milliseconds), and QEC efficiency (2:1 ratio on Quantinuum Helios). Silicon spin leads in potential fabrication density, cost scalability, and compatibility with classical electronics. The timescale comparison: trapped ions may deliver fault-tolerant computing by 2029–2030 (Quantinuum Apollo); silicon spin is unlikely to reach comparable logical qubit counts before the early 2030s, but could eventually produce far cheaper and more compact machines.

Silicon Spin vs. Neutral Atom

As I discussed in the neutral-atom article, these two modalities occupy opposite ends of the maturity-vs-scalability spectrum. Neutral atoms have 6,100 demonstrated qubits and 96 logical qubits; silicon spin has ~12 qubits and first logical operations. Neutral atoms operate at room temperature; silicon spin needs cryogenics (though milder than superconducting). Both share the advantage of identical qubits (atoms of the same isotope, or quantum dots on the same wafer, though silicon suffers from fabrication variability that atoms do not). The silicon pitch is long-term manufacturing economics; the neutral-atom pitch is “working now at scale.”

Silicon Spin vs. Photonic

Both modalities claim semiconductor fab compatibility, but through different physics. PsiQuantum‘s photonic Omega chipset is fabricated at GlobalFoundries’ 300 mm fab; silicon spin qubits run on imec’s and Intel’s 300 mm lines. The difference: photonic qubits use light on silicon photonic waveguides at room temperature (with cryogenic detectors), while silicon spin qubits use electron spins in silicon quantum dots at cryogenic temperatures. Photonic gates are probabilistic (fusion operations succeed with some probability); silicon spin gates are deterministic (exchange interactions work every time).

The manufacturing scaling argument favors silicon spin for compute density (quantum dots are smaller than photonic circuits and produce deterministic gates), but photonic systems may scale faster in total qubit count because their room-temperature operation avoids cryogenic cooling constraints entirely. PsiQuantum‘s million-qubit compute centers in Brisbane and Chicago represent a bet that photonic architectures, despite higher per-gate resource costs, can reach fault tolerance through sheer manufacturing volume. Silicon spin’s bet is that CMOS density and deterministic gates will ultimately produce more useful computation per square millimeter of chip area.

Advantages

CMOS fabrication compatibility. The defining advantage. Silicon spin qubits can be manufactured on the same 300 mm wafer lines used for classical processors and memory. This means access to the world’s most advanced lithography, metrology, and process control infrastructure. If qubit uniformity can be achieved at foundry scale, the cost-per-qubit could drop by orders of magnitude compared to any modality that requires specialized fabrication (superconducting circuits in quantum fabs, ion traps in UHV microfab, neutral-atom optical systems).

Extreme qubit density. A quantum dot is ~50 nm across. A superconducting transmon resonator is ~200 µm across. The theoretical density advantage is roughly 4,000:1. In practice, gate electrodes and wiring reduce this, but silicon spin qubits can achieve far higher qubit densities per unit chip area than any other solid-state modality. This matters for the millions-of-qubits regime that fault-tolerant cryptanalysis may require.

Cryo-CMOS co-integration. Silicon spin qubits and their classical control electronics are both silicon devices operating at cryogenic temperatures. They can potentially be fabricated on the same wafer or bonded in the same package, eliminating the room-temperature-to-millikelvin wiring bottleneck that constrains superconducting scaling. Intel’s Horse Ridge II, Diraq’s Emergence Quantum partnership, and Equal1’s SoC are all pursuing this integration path.

Higher operating temperature. Silicon spin qubits can operate at ~1 K, versus 10–20 mK for superconducting transmons. This permits helium-4-only cryostats (Bluefors XLDHe High Power), avoiding the helium-3 supply constraint, and provides 1,000× more cooling power for co-located control electronics.

Long coherence in purified silicon. In isotopically enriched ²⁸Si, electron spin T₂ reaches milliseconds and nuclear spin coherence reaches seconds to minutes. The ratio of coherence time to gate time supports thousands of operations per coherence window.

Fast gates. Exchange-based two-qubit gates operate at 10–200 ns, comparable to superconducting CZ gates. Silicon spin qubits do not suffer the speed penalty of trapped-ion or neutral-atom systems.

Disadvantages

Qubit count years behind. The largest demonstrated silicon spin processors have ~12 qubits versus 1,121 (superconducting), 98 (trapped ion), and 6,100 (neutral atom). The gap is not closing quickly. Reaching 50–100 controlled silicon spin qubits is a multi-year engineering effort involving simultaneous challenges in fabrication uniformity, control multiplexing, and crosstalk management.

Fabrication variability. Classical transistors tolerate significant variability because they operate digitally (on/off). Qubits require analog precision: each quantum dot’s charging energy, tunnel coupling, and resonance frequency must be tuned to specific values. Device-to-device variability on current wafers means each qubit needs individual gate-voltage calibration, a process that does not scale well to thousands of qubits without automated tuning algorithms and tighter process control than currently achieved.

Nearest-neighbor connectivity. Exchange coupling is short-range: only adjacent quantum dots interact. Long-range connectivity requires either electron shuttling (physically moving an electron through a chain of dots, demonstrated at 99.3% fidelity over 530 nm but still with overhead) or coupling via superconducting microwave resonators (demonstrated in research but not at production quality). This nearest-neighbor constraint means silicon spin qubits face the same SWAP-overhead problem as superconducting planar chips, and cannot natively implement the high-rate qLDPC codes that give trapped ions and neutral atoms their QEC efficiency advantage.

Cryogenic operation required. While milder than superconducting requirements (~1 K vs. 10 mK), silicon spin qubits still need cryogenics. This is a disadvantage versus neutral atoms (room temperature) and partially versus trapped ions (room-temperature vacuum chamber, though some detector subsystems need cooling).

Readout speed and fidelity. Spin readout via charge sensing is slower (1–100 µs) and lower fidelity (95–99%) than superconducting dispersive readout (99.5% in ~500 ns). RF reflectometry is closing the gap but is not yet as mature. Readout multiplexing (reading many qubits simultaneously) is less developed than in superconducting systems, where frequency-multiplexed readout resonators are standard.

No QEC at scale. The first logical operations and error detection were demonstrated in early 2026, but silicon spin has not yet demonstrated a logical qubit with lifetime exceeding the physical qubits, or below-threshold error correction. These milestones are years away at current progress rates.

Impact on Cybersecurity

Silicon spin qubits are unlikely to produce the first CRQC. Superconducting, trapped-ion, and neutral-atom systems all have multi-year head starts in qubit count and error correction demonstrations. But silicon spin qubits change the threat model in a subtler way: they change the second CRQC and every one after it.

If CMOS-fabricated quantum chips can be mass-produced at semiconductor-industry economics, then the cost and accessibility of quantum computing hardware drops to a level where CRQCs are no longer confined to nation-state laboratories or hyperscaler budgets. A CRQC-capable silicon spin chip manufactured at TSMC or Intel could, in principle, be purchased by any well-funded organization. The proliferation risk is different from a world where CRQCs require specialized $100 million facilities.

This is a long-term concern, not an imminent one. The Gidney 2025 estimate of ~1,400 logical qubits for RSA-2048 would require millions of physical silicon spin qubits at current overhead ratios (surface code at ~1,000:1). Even with the CMOS density advantage, fabricating and controlling millions of silicon spin qubits is a 2030s+ proposition. But the trajectory is worth tracking through my CRQC Quantum Capability Framework, particularly the engineering scale and manufacturability dimension.

The practical response remains the same: PQC migration now. Regulators, insurers, and clients are setting deadlines that don’t depend on which modality arrives first.

Future Outlook

2026–2027. Diraq and Intel push toward 50+ qubit devices on 300 mm wafers. SemiQon scales its 12-qubit 1D array. The first surface-code error correction experiments on silicon spin qubits become feasible if uniformity challenges are addressed. The Nature Reviews CMOS compatibility assessment sets the research agenda for which fabrication processes need adaptation. Cryo-CMOS co-integration (Horse Ridge III, Emergence Quantum mK-CMOS, Equal1 SoC) enters its first integrated demonstrations with working qubits.

2028–2030. If the CMOS thesis holds, silicon spin qubit arrays reach 100–1,000 qubits, a scale enabled by foundry fabrication throughput rather than heroic lab effort. Electron shuttling matures as a mechanism for extending connectivity beyond nearest neighbors. The first error-corrected logical qubits on silicon spin hardware are plausible in this window. Intel, if it fully commits fabrication resources, could accelerate this timeline significantly.

2030s. This is where silicon spin qubits either justify their thesis or don’t. If millions of qubits can be manufactured on wafer-scale silicon with sufficient uniformity and integrated cryo-CMOS control, the modality produces the cheapest, densest, and most manufacturable quantum processors in the world. If fabrication variability cannot be tamed at scale, silicon spin remains a niche research platform while superconducting and neutral-atom systems deliver fault tolerance through other manufacturing approaches.

The uncertainty is real. ECC has been under-researched relative to RSA in quantum cryptanalysis, and silicon spin’s potential to produce cheap, accessible quantum hardware should influence how urgently organizations treat the post-quantum transition. The existence of a plausible manufacturing path to mass-produced CRQCs, even if it is a decade away, strengthens the case for acting now.