Table of Contents
Introduction
In The Dark Horse on March 31, I argued that silicon spin qubits had assembled every building block for fault-tolerant quantum computing while the field watched neutral atoms. I closed with five capabilities silicon still had to demonstrate, in the order I expected them to arrive, and I attached a specific “watch for” criterion to each so the list could be graded later rather than admired.
Four months later, silicon spin had a Nature cover, a foundry milestone, and an extraordinary run of coverage. So I went back and graded the list.
Two cleared. One moved partway. One did not move. And one, the item I had called the decisive proof point, was passed on a technicality by a result that leaves the thing I meant to measure exactly where it was in March. That last outcome is the most useful thing on the scorecard, because a criterion that can be satisfied without the underlying question moving is a badly written criterion, and I wrote it.
None of this is a knock on the results, which are excellent, or on the people who produced them. It is an audit of my own test, and a proposal for a better one.
Grading the Five
Item one: mid-circuit measurement and real-time feedback. I called this the single most important missing capability, since silicon’s encoded-error work to that point had relied on destructive parity projection in postprocessing rather than repeated real-time syndrome extraction. What I said to watch for was a silicon experiment showing non-destructive, mid-circuit syndrome extraction.
Cleared. The HRL Laboratories paper, published online July 29 and on the cover of Nature’s July 30 issue, which I covered in detail at the time, runs 200 rounds of syndrome extraction with leakage reduction units that reset data qubits conditional on their having left the computational subspace. Two qualifications the coverage skipped. Readout is still digitized at room temperature, and the paper is explicit that the processor needs room-temperature connections for digital communication, readout and static biases. What runs autonomously inside the fridge is the pulse program. Repeated mid-circuit syndrome extraction under cryogenic pulse control, then, rather than a closed cryogenic measurement-and-feed-forward loop.
Item five: cryo-CMOS integration. I said to watch for qubits controlled by co-located cryogenic CMOS without performance degradation.
Cleared, and this is the least equivocal result on the list. A controller of roughly 70 million transistors in a commercial 130-nanometre RF CMOS process, at 4 kelvin, consuming 3.5 watts or less in typical operation, generating every time-varying control signal for a 54-dot array configurable to host up to 18 exchange-only qubits, delivered through a 296-trace superconducting ribbon cable. Exchange-only performance advanced by an order of magnitude against the prior state of the art rather than degraded. This is what the field has been promising since Intel’s first Horse Ridge paper.
Item two: repeated error correction cycles with net benefit. The criterion matters here. What I wrote was to watch for a silicon experiment showing that logical qubit lifetime exceeds physical qubit lifetime under repeated error correction. Break-even, in other words.
Partial. HRL’s distance-5 repetition code, running on seven qubits, reached a logical error rate near 5 × 10⁻³ against the average of distance-3 subsets drawn from the same data, a scaling factor Λ₅/₃ = 4.7. Error suppression improving with code distance is what fault tolerance requires and it is a real result. It is not break-even, and a repetition code tests one error type at a time rather than the full surface-code test Google’s Willow processor passed in 2024. HRL claims no more than it showed. The paper also reports unexplained fluctuations in the distance-5 error rate absent from its other datasets. The Shenzhen logical-operations result points the same way: average logical coherence around 208 microseconds against an average physical coherence around 523 microseconds, and the paper’s physical average excludes its two weakly coupled nuclei. Encoding is not yet protecting.
Item three: scaling beyond a single cluster. My criterion named names. SQC’s 11-qubit processor had connected two donor registers; the next step was arrays of four, eight, sixteen registers, and I said to watch for SQC or SZIQA publications demonstrating multi-cluster arrays, citing the SZIQA donor-cluster preprint as the signal that work was underway.
Did not move. What arrived instead was an 18-qubit modular array from Dijkema, Zhang and colleagues at Groove Quantum and QuTech, on an extendable two-by-N architecture with simultaneous initialization, control and readout across every qubit, average single-qubit fidelity of 99.8% and median of 99.9%. Excellent work. It is germanium hole spins rather than silicon, gate-defined dots rather than donor clusters, a different group, and still a preprint. It shows a modular spin-qubit architecture scaling in a neighbouring material. It is not the silicon donor-cluster array I said to watch for, and counting it would be grading on a curve. The SZIQA preprint I pointed at has since been revised and retitled, and remains an architecture proposal with analytical and numerical results rather than a fabricated multi-register array.
Item four: foundry qubits reaching logical operation. This is the one that exposed a defect in my own test.
I wrote that the field should watch for “any foundry-fabricated silicon device demonstrating error correction or algorithmic performance above threshold.” HRL’s qubit gates were patterned in a proprietary 200-millimetre wafer foundry process, and its processor ran repeated syndrome extraction with logical error suppression improving as code distance increased. Read literally, that clears the criterion. It certainly did not leave it untouched, and my first draft of this assessment scored it “did not move,” which was wrong.
What I meant is in the March text around the criterion, where item four is about proving that industrially manufactured qubits can do what bespoke qubits have done, with the Diraq/imec 300 mm line as the reference point. HRL is the bespoke side of that comparison. So the criterion and its purpose came apart, and I cannot grade the purpose while claiming to grade the criterion.
Meanwhile the industrial lines moved without touching error correction. Andreas Nickl, Tuomo Tanttu and the Diraq and imec teams operated eight qubits in a linear chain on imec’s 300 mm process in Leuven, published in Nature Communications on July 9. Polysilicon gates at 90 nanometre pitch, an isotopically enriched epilayer carrying 400 parts per million of residual silicon-29, single-electron transistors at each end for readout. All eight individually tuned and coherently controlled as four double-dot pairs, with a two-qubit gate demonstrated on one adjacent pair; entangling control across the full chain remains open. It is the most complete published demonstration of high-fidelity multi-qubit operation from an industrial 300 mm silicon process, though Intel has fabricated and individually controlled a larger 12-dot array. It contains no error correction, no logical qubit, no syndrome extraction, and no algorithm above threshold.
So: two cleared, one partial, one open, one passed-as-written-but-not-as-meant. The pattern underneath is that the field moved fast wherever a bespoke device could carry the result, and the criterion that was supposed to detect exactly that turned out not to.
Why the Test Failed, and What Replaces It
My first attempt at explaining the gap was that HRL screened its dies. The Methods say wafers are probed to select high-yielding die before dicing and bump bonding, and I initially read that as the opposite of what the CMOS thesis needs.
That reading was wrong. I nearly published it, so let me correct it here rather than quietly. Wafer sort, die sort and known-good-die selection are ordinary semiconductor manufacturing, and the July Diraq and imec paper makes the point without needing the general principle: its author-contributions statement says the imec team performed an initial electrical device screening at wafer scale. Screening is part of both stories. Intel bins parts; every foundry throws away dies. A viable silicon spin process does not have to eliminate screening. It has to produce enough known-good dies that fabrication, test, packaging and commissioning stay economical. Screening is not the problem. Undisclosed yield is.
The contrast I drew on the other side was also too clean. I have written before that Diraq and imec tested devices selected at random from a production wafer, and that framing comes from the companies’ joint announcement. The peer-reviewed paper says something more careful: the wafer carried several designs, the team chose the design it estimated would have optimal device parameters, and it tested four devices of that design. That is real evidence of reproducibility within a chosen design. It is not a wafer-level yield distribution, and it is not the pure unscreened control I implied.
What does distinguish the results is in the Methods sections, and it is not about screening at all. It is about how the qubit gates get written.
HRL’s Methods say the qubit gate design, at a 70-nanometre minimum feature pitch, was patterned with electron-beam lithography, as were all three minimum-pitch routing levels. Optical lithography handled the ohmic contacts and the larger-pitch layers above, and the back end is industry-standard. I initially took that as an HRL-specific caveat. It is not. imec’s Methods for the eight-qubit device say optical and electron-beam lithography were combined to balance throughput with patterning precision, and that the triple-layer overlapping polysilicon gate stack was defined by electron-beam lithography. The September 2025 unit-cell paper describes the same flow, and frames the combination as what gives the line fast fabrication cycles and design flexibility.
E-beam lithography is serial. It writes features one at a time with a focused beam, which is why it is the tool of choice for prototypes, mask-making and research devices, and why no high-volume logic part has ever been made with it. The strongest form of the silicon argument is that quantum chips can ride the cost curve of optical lithography, where a single exposure patterns an entire field and the marginal cost of the millionth device approaches zero. Neither of the two devices at the centre of this year’s coverage rides that curve at the layer that defines the qubit. For a pilot line iterating on gate geometry, e-beam is the sensible engineering choice and nobody should pretend otherwise. It is a choice about development speed, not a claim about production economics, and imec says as much.
One silicon spin platform does pattern its qubit gates with high-volume tooling. Intel’s Tunnel Falls devices are fabricated with immersion and EUV lithography and production-level process control, and the qubit, SET and centre-screening gates are defined in a single EUV pass using an industry-standard replacement metal gate flow. That is the manufacturing proposition the cost curves are written about.
So the evidence is spread across three axes and no silicon device holds more than two of them. HRL has repeated error correction and cryogenic control, on e-beam-patterned qubit gates and dies selected after probing. Diraq and imec have the strongest multi-qubit operation from an industrial 300 mm line, also on e-beam-patterned qubit gates, with no error correction. Intel has genuinely high-volume-compatible patterning and wafer-scale characterization, with no error correction and no benchmarked multi-qubit gate performance. I have found no published experiment combining net-beneficial error correction with qubit gates patterned by high-volume-compatible lithography, and none disclosing the yield distribution that would let anyone price it.
Which is the replacement test, stated so it cannot be passed on a technicality:
Repeated error correction with net benefit, on representative silicon spin devices whose qubit gates were patterned by high-volume-compatible lithography in an industrial 300 mm process, with the die-selection protocol disclosed and wafer-level distributions published linking error-correction-relevant qubit parameters to known-good-die yield.
Screening may stay. What has to become visible is how devices were chosen, how many passed, what the tails look like, how much cryogenic characterization each one needed, and what a known-good die capable of error correction actually costs.
The Line Item Nobody Prices
Diraq has done something most of the industry avoids, which is to publish its cost thinking and invite people to argue with it. Their June post sets out three acts: cryogenics dominates in 2026, classical compute catches up around 2029, and by the early 2030s a system with millions of qubits trends toward less than a dollar per qubit. The chip itself falls below a cent per qubit. Roughly a thousand dollars per logical qubit goes to decoders, GPU clusters and cryogenic electronics. Diraq argues that its 8-qubit chip and its projected ten-million-qubit chip would be “all roughly the same size,” which is why the cryogenic cost stays flat while the qubit count climbs.
Publishing this was the right call and I wish more vendors did it. A number you can check is worth more than a roadmap slide with arrows on it. Andrew Dzurak’s team has also earned the right to make an economic argument, having produced the results that give the CMOS thesis its evidence base and having taken it through DARPA’s Quantum Benchmarking Initiative to Stage B, an A$20 million equity investment from Australia’s National Reconstruction Fund Corporation in February, and a Commerce Department letter of intent for up to $38 million in CHIPS research funding alongside a manufacturing engagement with GlobalFoundries.
So I want to put my question as a question, because it may well have an answer I have not seen.
The published cost narrative prices fabrication, cryogenics and decoding. It discloses no separate assumption for device commissioning, calibration or recalibration. And calibration is what the 2026 experimental literature keeps identifying as the current limit on devices in this modality.
Consider the result that produced the highest parallel-control fidelities yet reported in silicon. Yi-Hsien Wu, Leon Camenzind and colleagues in Seigo Tarucha’s group at RIKEN, working with Giordano Scappucci at Delft and Hsi-Sheng Goan at National Taiwan University, drove five silicon spin qubits through a single shared microwave line. Individual π/2 gate fidelities came in well above 99.99%, some approaching 99.999%, and held above 99.99% through three simultaneous qubits. Under fully parallel five-qubit operation they settled at 99.9%, with the authors attributing part of the residual drop to drive-induced decoherence at higher microwave power. The cause of the degradation was AC Stark shifts from the shared drive, and the fix is pairwise phase compensation. Elegant work, and still a preprint.
The authors are explicit that their scheme needs only pairwise calibrations rather than full crosstalk characterization, which turns an exponential problem into a quadratic one, and they argue the overhead shrinks further for well-detuned pairs. What the paper does not analyse is what that quadratic count costs in practice. Five qubits means ten unique pairs. A hundred means 4,950. A thousand means roughly half a million. Whether that becomes a wall-clock problem depends on how often recalibration is needed and on structure nobody has published. What can be said is that the field’s best parallel-control result is also its clearest published measurement of fidelity falling as qubits are operated together, and it sits alongside HRL’s finding that its dominant errors are extrinsic: static magnetic field gradients and contextual pulse miscalibration rather than anything intrinsic to the qubits.
Gordon Moore’s 1965 argument was economic before it was technological. Cost per component falls as integration rises, and the minimum-cost point shifts upward as the process improves. Classical manufacturing already pays for wafer sort, binning, burn-in and final test, so testing is not the objection. What it does not require is continuous analogue commissioning of every transistor. Silicon spin has to show that qubit tune-up eventually behaves like automated chip-level test rather than per-device laboratory commissioning.
Which sharpens the question. Does the Diraq curve assume per-device tuning falls away through process control, or that it stays roughly constant per chip through automation? Those are different claims with different capital requirements, and the space between them is where the dollar-per-qubit number lives.
A serious answer exists and I take it seriously. Jonas Schuff, Miguel Carballido and colleagues published fully autonomous tuning of a spin qubit in Nature Electronics in February, taking a device from grounded to Rabi oscillations using deep learning, Bayesian optimization and computer vision with no human in the loop. It succeeded in 10 of 13 end-to-end trials, with most runs concluding within three days, against the weeks or months the authors associate with expert manual commissioning. Q-CTRL and Equal1 announced a partnership in April to integrate autonomous calibration into Equal1’s silicon systems, which is a product programme rather than a published demonstration at scale. If tuning becomes cheap, my calibration objection narrows sharply, though yield, cryogenic test time, interconnect and drift would remain.
One qualification on the Schuff result I would rather state than have a reader find. The device was a germanium-silicon core-shell nanowire, not silicon MOS, so transfer to the foundry platform is an inference rather than a demonstration.
I have a soft spot for this particular line of research, because tuning a quantum dot device used to be somebody’s entire doctorate. Months at a screen, nudging gate voltages by millivolts, chasing a charge stability diagram into the corner where it behaves. A generation of spin qubit physicists learned the platform that way, and not one of them will miss it.
My position is that automation gets the field to hundreds of qubits and is the main reason 2027 will look fast. Whether it gets to millions is open. Architectural regularity, shared control lines, sparse calibration graphs and factory characterization could all cut the burden faster than device count grows. Until that is shown, nobody has established that commissioning and recalibration become chip-constant, or even sublinear, at useful scale.
The Dot Is Not the Whole Density Story
A silicon quantum dot confines a single electron in a region roughly 50 nanometres across, which is the number the density argument rests on and is genuinely remarkable next to a superconducting transmon at a couple of hundred micrometres.
Then look at what has to reach the dot. Diraq’s imec chain sits at 90 nanometre gate pitch, already nearly twice the dot. HRL’s superconducting ribbon cable, the piece of engineering that made autonomous pulse execution possible, carries 296 coaxial lines in a ribbon about a centimetre wide, with signal wires on a 15 micrometre pitch. Roughly three hundred times coarser than the object being controlled.
These are not directly comparable measures. Dot diameter is a confinement scale, gate pitch is a layout scale, and ribbon pitch is an interconnect scale that has to carry signal integrity and shielding along with the signal. As an order-of-magnitude illustration, though, the point holds: without multiplexing or local control, every independently addressed gate electrode needs a route out of the array and across a thermal boundary. Crossbars, shared drive lines and cryogenic electronics at the qubit plane all exist to break that relationship, and HRL put a 70-million-transistor controller inside the fridge for exactly this reason. A claim that an 8-qubit chip and a ten-million-qubit chip are the same size is a claim about multiplexing, fan-out and defect-tolerant topology, not about the diameter of a quantum dot, and it should be argued on those terms.
Shuttling Electrons to Get Around the Connectivity Problem
Static exchange coupling is local, which leaves silicon spin with the SWAP overhead that constrains planar superconducting chips and makes the high-rate qLDPC codes that give trapped ions and neutral atoms their error-correction efficiency expensive to implement, since routing overhead can eat the rate advantage.
The proposed fix is to move the electron. Brennan Undseth and colleagues at QuTech and TU Delft published the companion paper to HRL’s in the same issue, shuttling a mobile spin along a bus with four stationary interaction sites over a characterized 1.2-micrometre round trip, performing parity checks up to weight four that form a surface-code stabilizer plaquette, and building a five-qubit GHZ state, among the largest yet made with gate-defined semiconductor spins. Yuta Matsumoto, Maxim De Smet and co-authors separately demonstrated two-qubit logic and teleportation with mobile spins earlier in 2026.
Reconfigurable connectivity in a solid-state platform is a real advance and it addresses the objection I would otherwise rank second after manufacturability. The demonstrated numbers also show how early it is: shuttling fidelity around 97.7% against an identity operation, weight-four parity-check accuracies in the seventies and sixties of a percent depending on basis, and a postselected logical-state fidelity in the low sixties. The paper budgets errors for the circuits it demonstrates. What is missing is the harder accounting: a full-cycle budget showing that shuttling, idling, loading, measurement and two-qubit gates together stay below threshold under repeated operation at code distances that matter. Connectivity is answered in principle and open in practice.
Both Logical Milestones on My March List Came Out of Shenzhen
The universal logical gate set on silicon was demonstrated by the Shenzhen International Quantum Academy with the Southern University of Science and Technology. Chunhui Zhang and colleagues, in a group led by Dapeng Yu and Yu He, published in Nature Nanotechnology on March 23: five phosphorus donor nuclear spins in isotopically purified silicon-28, the [[4,2,2]] code encoding two logical qubits, a universal gate set including a non-Clifford T gate implemented by gate-by-measurement, and a magic state prepared above the Bravyi-Kitaev distillation threshold. A variational quantum eigensolver ran on the encoded qubits to compute the ground-state energy of water. The error detection result from January came from the same team. The [[4,2,2]] code detects errors rather than correcting them, and the logical gate fidelities sit well below the underlying physical ones, so this is an encoded-operations milestone rather than fault-tolerant computation.
Both of the logical milestones on my March list therefore came from one group in Shenzhen, using a fabrication technique that needs an ultra-high-vacuum STM and no advanced logic node.
Set that against where the manufacturing route’s dependencies sit. imec in Leuven. GlobalFoundries, named in a Commerce Department letter of intent for $375 million in planned quantum-foundry funding. Intel’s 18A process, now the target of a NEDO-funded Hitachi, Intel Japan and AIST programme to build a spin-qubit process design kit. STMicroelectronics at Crolles. Soitec and ASP Isotopes on enriched silicon-28. The September 2024 BIS interim final rule added quantum computing items, components, materials, software and technology to the Commerce Control List, so this supply chain already sits inside an export control regime.
The tempting conclusion is that controls bear on the route that needs the fab and not on the route that doesn’t. I do not think that holds, and I am flagging it rather than asserting it. Atomic-precision fabrication still depends on enriched silicon-28, ultra-high-vacuum instrumentation, precursor handling and metrology, and technology controls, deemed-export provisions and end-user restrictions reach controlled technical know-how regardless of node. Whether export policy favours one route depends on the control status of equipment, materials, process knowledge and the resulting system, not on fab access alone. I will take that apart properly in a separate piece; the general form of the argument is in Quantum Sovereignty.
Running the CRQC Framework Over It
My CRQC Quantum Capability Framework exists to stop this kind of assessment collapsing into a qubit count, so let me apply it as a portfolio view rather than walking every capability, which I already did for HRL specifically.
Silicon spin is among the strongest modalities on engineering scale and manufacturability while trailing on quantum error correction, below-threshold operation and qubit connectivity. Most competing platforms show the inverse emphasis: stronger public error correction demonstrations, weaker evidence that whole systems can be reproduced economically at the physical qubit counts required. On decoder performance, I have found no published silicon spin experiment that integrates and benchmarks a low-latency decoder at meaningful scale; HRL used a naive parity-check decoder for its repetition-code data.
That profile has a specific consequence for sequencing. A manufacturability lead buys nothing until the error correction capabilities arrive, because a line that yields a million mediocre qubits has produced a million mediocre qubits. Error correction without manufacturability caps out at machines you can count. The platform that reaches a CRQC first will be whichever closes its own gap first, and silicon’s gap is the harder kind to schedule, because it requires two independently difficult things to be true of the same chip.
One capability cuts in silicon’s favour and I want it on the record, since I made a good deal of it in March. The biased noise the Shenzhen experiments revealed, where phase-flip errors dominate because nuclear spin relaxation in silicon-28 is long enough to be negligible over the experimental window, admits tailored codes with thresholds well above the standard symmetric-noise figure. I worked through the consequences in a separate analysis. The measurement is specific to a donor nuclear-spin architecture and should not be generalized to electron-spin devices in SiMOS or Si/SiGe, which have different noise channels. Where it does apply, symmetric-noise resource estimates like Gidney’s may be conservative, provided the bias survives gates, measurement, leakage, transport and scaled control.
What This Changes for Security Planning
Nothing this quarter. Seven qubits running a repetition code and two logical qubits computing the ground state of a water molecule are not a threat to anything, and the distance from there to the roughly 1,400 logical qubits and under a million noisy physical qubits in Craig Gidney’s architecture-specific 2025 estimate for RSA-2048 is not a gap that closes by surprise.
The longer-run effect is on a question most threat models never ask, because most threat models are built around whether a CRQC exists rather than how many exist.
Assume some platform gets there. If the winning machine is a bespoke installation costing hundreds of millions and needing a national laboratory to run, then for years afterward the world contains two or three, they belong to states, and they get pointed at targets worth the operating cost. If the winning machine comes off a high-volume line, the interval between the first CRQC and the fiftieth is short and the unit cost falls the whole way down.
That interval sets three things a CISO has to plan around. How long harvested archives stay expensive to decrypt rather than routine. How long the capability to forge signatures retroactively stays confined to actors with diplomatic exposure and something to lose. And whether a root of trust with a twenty-year life is exposed to two adversaries or two hundred.
My assessment is that silicon spin is unlikely to produce the first CRQC, and that it is one of the strongest candidates to compress the cost curve between the first machine and widespread replication, if the manufacturing thesis holds. That is a 2030s argument and I am labelling it as one, because dressing it up as an imminent threat would be exactly the Q-FUD I spend half my time arguing against.
It also changes nothing about what to do in the next twelve months. I have made this case enough times that regular readers can recite it: the migration clock stopped being set by Q-Day estimates the moment regulators, insurers and large customers started writing their own dates into contracts. Start with discovery, get a cryptographic inventory, work the migration framework. The modality race is interesting. It is not an input to your programme plan.
What Would Settle It
The replacement test above is the one carrying the economics, and I am stating it in advance this time so it can be graded rather than reinterpreted: net-beneficial repeated error correction on representative silicon spin devices whose qubit gates were patterned with high-volume-compatible lithography, with the selection protocol disclosed and wafer-level parameter distributions published.
Item three stays open too, and the germanium result makes it more interesting rather than less. If a donor-cluster array in silicon reaches four or eight registers with maintained fidelity, the atomic-precision route stops looking like a throughput dead end and starts looking like a second path to scale.
A third result would inform this more than either: yield data. Charging energies, tunnel couplings, resonance frequencies, gate fidelities, the spread and the tails, across a full wafer rather than the dies that made the paper. Intel comes closest, having published full-wafer automated cryogenic probing with most quantum-dot devices tuned into the single-electron regime, but those are electrostatic and tune-up distributions. I have found no public wafer-level distribution linking error-correction-relevant qubit performance to known-good-die yield anywhere in the modality. Cryogenic wafer-level testing is expensive and characterization is incomplete, so the absence is explicable. It is also the single number that would turn the dollar-per-qubit argument into checkable arithmetic.
All three are plausible inside twenty-four months. I would rather have any one of them than another ten papers about fidelity records, and I say that as someone who has spent this entire article quoting fidelity records.
