Table of Contents
August 1, 2026 – On July 23, 2026, IBM announced a definitive agreement to acquire HRL Laboratories from Boeing and General Motors. Eight days later, the cover of Nature featured the reason why.
HRL’s quantum team published a paper demonstrating something no group had shown before: a silicon quantum processor that generates all of its own time-varying control signals inside the cryostat, runs repeated rounds of error correction, and does both without real-time input from room-temperature electronics. The system integrates three separately fabricated semiconductor components into a single quantum processing unit: an 18-qubit exchange-only spin chip at millikelvin temperatures, a custom 70-million-transistor CMOS controller at 4 kelvin, and a 296-trace superconducting ribbon cable connecting the two. Once initialized, it runs autonomously.
The bottom line for organizations evaluating quantum timelines: HRL has demonstrated that the wiring bottleneck constraining quantum computer scaling has an engineering solution, and IBM just paid an undisclosed sum to own it. The system is small (seven qubits used for the largest demonstration) and the error rates are not yet competitive with the best superconducting or neutral-atom results. But the architecture addresses a problem that every modality must eventually solve, and it does so with components fabricated entirely using semiconductor wafer processes.
The News
On July 29, 2026, Nature published “A digitally controlled silicon quantum processing unit” as its cover story. The paper was authored by the HRL Quantum Team and collaborators at HRL Laboratories (Malibu, California) and Boeing, with Jacob Z. Blumoff, Thaddeus D. Ladd, and Matthew D. Reed as corresponding authors.
At the core of the QPU sits a quantum chip with 54 exchange-coupled quantum dots distributed across three rails, configurable to host up to 18 exchange-only (EO) qubits. EO qubits encode information in the collective spin state of three electrons confined in three quantum dots, using only baseband voltage pulses for control. No microwave drives or magnetic field gradients are required, which makes them compatible with the low-power, digital-like signals a cryogenic CMOS controller can generate.
Controlling those qubits is a mixed-signal system-on-chip fabricated in a commercial 130-nm RF CMOS process. It operates at 4 K with power consumption of 3.5 W or less, within the cooling budget of the commercial dilution refrigerator’s 4 K stage. It features six independent instruction sequencers, 366 DACs, 78 pulse generators, and on-chip pseudo-random number generators for executing randomized benchmarking autonomously. Its DACs achieve less than 10 μV RMS step size and noise density below 1.4 μV/√Hz.
Connecting these two components, a superconducting ribbon cable routes 296 traces through a niobium-on-polyimide structure with 15-μm wire pitch. Crosstalk between nearest-neighbor wires stays below −90 dB at 1 GHz and below −80 dB at 10 GHz. The cable conducts less than 10 μW of heat from the 4 K stage to the mixing chamber, maintaining qubit electron temperatures at an average of 150 mK across the device.
Qubit performance advances the exchange-only state of the art by an order of magnitude. Mean single-qubit gate errors measured 2×10⁻⁴ and mean CNOT errors measured 3.5×10⁻³, with the lowest reproducible CNOT error reaching 9×10⁻⁴. Intrinsic device charge noise improved by approximately a factor of ten over previous results, and intrinsic noise collectively would contribute only 0.02% to absolute CNOT error. The dominant error sources are extrinsic: static magnetic field gradients and contextual pulse miscalibration from signal generation and transmission.
The paper validated the integrated system with three multiqubit demonstrations:
A distance-5 repetition code using seven EO qubits, executing up to 200 rounds of syndrome extraction (1,805 initializations, 805 measurements, and 335,422 exchange pulses per 200-round instance). The distance-5 code achieved a logical error rate of 5.0×10⁻³, compared with 2.3×10⁻² for distance-3 subsets, yielding a distance improvement factor Λ₅/₃ = 4.7. Leakage reduction units maintained a stable detector event fraction across rounds.
For the distance-3 repetition code, using four qubits, the logical error rate with leakage reduction was 3.2×10⁻³. Simulations calibrated on measured gate error rates and device noise parameters matched the experimental logical error rate to within 15%.
Finally, a [[4,2,2]] quantum error detecting code using six physical qubits, implementing two logical qubits with three rounds of syndrome extraction. After post-selecting on all error-detecting measurements (rejecting approximately 77% of experimental shots), the code achieved a logical fidelity of 0.95 across all four initial states. Without post-selection, the logical fidelity dropped to 0.59. The gap between 0.95 and 0.59 confirms that the error detection is working.
The same Nature issue carried a companion paper from Brennan Undseth and colleagues at Delft University of Technology and QuTech. Their approach is architecturally different: a spin-shuttling system that physically transports a single qubit approximately 1.2 micrometers between four stationary qubit locations. That team achieved weight-four parity checks forming a surface-code stabilizer plaquette and generated a five-qubit GHZ state, the largest such state constructed with gate-defined semiconductor spins. Together, the two papers provided Nature with its first-ever silicon quantum computing cover story.
IBM’s acquisition of HRL, announced on July 23 for an undisclosed price, is expected to close by the end of the third quarter of 2026. Boeing and General Motors, HRL’s current owners, will continue partnering with IBM on quantum applications and advanced technology development. Jay Gambetta, IBM’s Director of Research, told Reuters that electron spin’s size advantage will “start to matter” once IBM’s superconducting Blue Jay system arrives in 2033, and that “the future is going to be spins, or superconducting, or possibly a combination of them.”
My Analysis
This paper is the most complete systems-integration demonstration from any silicon spin-qubit group to date. It is also, measured against the question I care about most on this blog, the most interesting silicon spin result in terms of what it means for the path to a cryptographically relevant quantum computer (CRQC).
I want to separate what the paper actually shows from what the press coverage implies, because they are different things.
What the Paper Shows
The headline result is not the gate fidelities, though they are good. It is the integration. HRL took a qubit chip, a controller chip, and a cable, fabricated each with semiconductor wafer processes, packaged them inside a single commercial cryostat, and ran a quantum error correction circuit that required no real-time classical intervention. The system generates its own control signals, runs its own benchmarking sequences using on-chip random number generators, and executes hundreds of syndrome extraction rounds autonomously.
That is a different kind of milestone than demonstrating a new surface code distance or a record gate fidelity. It is a systems engineering demonstration, and systems engineering is where quantum computing either succeeds or fails at scale. I wrote an entire book about this, so I will admit my bias up front: I think the integration story here is more important than any single number in the paper.
Every qubit modality faces the wiring bottleneck. Today’s superconducting quantum computers rely on racks of room-temperature electronics connected to the qubit chip through hundreds of coaxial cables that each carry heat into the cryostat. Scaling to millions of qubits with this architecture faces a ceiling: the cables consume the refrigerator’s thermal budget before you run out of ideas for what to compute. Solutions have been discussed for years, including cryo-CMOS controllers, multiplexed readout, and photonic interconnects. What HRL has done is build one of those solutions, shown it works with real qubits running a real error correction circuit, and published the evidence in Nature.
HRL’s specific architecture choices are well-matched to this problem. Exchange-only qubits need only baseband voltage pulses (sub-nanosecond switching between DC levels), which are structurally similar to digital signals. That compatibility with standard digital logic is what makes the cryo-CMOS approach tractable for this modality. A superconducting transmon qubit, by contrast, requires shaped microwave pulses at GHz frequencies, which demand more power and more sophisticated signal generation at cryogenic temperatures. HRL chose a qubit type that simplifies the control problem, and then built the controller to match it. Good engineering.
Charge noise numbers deserve attention. The paper reports intrinsic device charge noise more than an order of magnitude lower than HRL’s previous SLEDGE technology, with intrinsic noise contributing only 0.02% to CNOT error. The gap between intrinsic device performance and measured gate performance is dominated by what the authors call “extrinsic” sources: signal integrity issues in the cryo-controller and interconnect, including pulse miscalibration and inter-symbol interference. Approximately 80% of detection events in simulation come from a quasi-static miscalibration error term the team had to add to make simulations match experiment.
This is actually encouraging for anyone tracking the path to fault tolerance. It means the qubit physics is ahead of the systems engineering. The qubits themselves could support lower error rates than the integrated system currently achieves. Signal integrity, pulse calibration, and magnetic hygiene are engineering problems with known solution paths, not physics barriers. When I assess CRQC timelines using my CRQC Quantum Capability Framework, I distinguish between physics-limited performance (where new scientific discoveries are needed) and engineering-limited performance (where known techniques need to be applied at higher precision). HRL’s system is clearly in the second category. That distinction affects how I estimate the pace of future improvement.
What the Paper Does Not Show
Seven qubits, not seven hundred. The largest demonstration used seven of the 18 available EO qubits for a distance-5 repetition code. The paper does not run a surface code, which is the error correction architecture most groups consider necessary for fault-tolerant computation. The distance improvement factor Λ₅/₃ = 4.7 is measured between distance-3 and distance-5 repetition codes, which test only bit-flip or phase-flip errors, not both simultaneously. Google’s Willow processor demonstrated below-threshold scaling on an actual surface code across multiple distances. That is a harder test, and HRL has not attempted it.
Post-selection rates tell their own story. In the [[4,2,2]] quantum error detecting code, approximately 77% of experimental shots are discarded. After throwing away three-quarters of the data, the remaining shots achieve 95% logical fidelity. That is a high discard rate by the standards of other modalities: Google’s surface code experiments retain all shots, and trapped-ion demonstrations typically post-select at far lower rates. HRL’s authors are transparent about this, and the code is error-detecting rather than error-correcting (it identifies errors but cannot fix them), so post-selection is the intended operating mode. But it means the system is not yet performing the kind of real-time, autonomous error correction that fault-tolerant operation requires.
Unexplained fluctuations in the distance-5 data also deserve scrutiny. The supplementary materials describe “spikes in detection events” lasting tens of milliseconds, where three of four detectors simultaneously showed elevated error rates. The team attributes these to some unidentified microscopic event causing correlated SPAM errors, and they did not appear in the distance-3 or [[4,2,2]] experiments. Correlated errors at unpredictable intervals are the kind of system stability issue that matters increasingly as circuit depth grows.
And the paper’s own simulation methodology makes a revealing concession. To match their simulations to experimental data, the authors added an “ersatz quasi-static miscalibration” parameter, essentially a fudge factor that represents the contribution of error sources they cannot yet model from first principles. They acknowledge this openly: “A quantitative model of the pulse-angle contextual miscalibration errors from the cryo-controller, interconnect, and package is difficult to achieve a priori.” When the dominant error source requires an empirical fitting parameter rather than a predictive model, there is meaningful engineering work remaining before the system can be systematically optimized.
The CRQC Framework Lens
Running this through my CRQC Quantum Capability Framework:
B.1 Quantum Error Correction: The paper demonstrates repetition codes (classical error correction) and a [[4,2,2]] quantum error detecting code. It does not demonstrate quantum error correction in the full surface-code sense. Capability rating: demonstrated at proof-of-concept level, not at the operational scale needed for CRQC.
B.3 Below-Threshold Operation: The Λ₅/₃ = 4.7 distance improvement factor shows error suppression with increasing code distance, but in a repetition code only. Below-threshold operation in a surface code, which tests both error types simultaneously, has not been shown. This is the metric that matters most for CRQC viability, and HRL’s exchange-only encoding makes the mapping between repetition code performance and surface code performance less direct than for single-spin qubits. The three-spin encoding introduces leakage into a non-computational subspace, which the team mitigates with dedicated leakage reduction units. The effectiveness of these LRUs at the scale a surface code requires is an open question.
D.2 Decoder Performance: The paper uses a naive parity check decoder, not a minimum-weight perfect matching decoder or a more sophisticated option. Real-time decoding at the speeds error correction requires has not been demonstrated.
E.1 Manufacturability: This is where the paper makes its strongest contribution. All three components (qubit chip, controller, ribbon cable) are fabricated using semiconductor wafer processes. The qubit chips show wire functional yields where more than 80% of devices exhibit 170+ passing lines out of 188 total, and the paper reports wafer-scale fabrication with 100% interconnect yield for the ribbon cables. The controller is manufactured at a commercial CMOS foundry. If silicon spin qubits reach the fidelity levels needed for fault tolerance, the manufacturing infrastructure to produce them already exists, in a way that does not apply to superconducting qubits (which require specialized Josephson junction fabrication) or trapped-ion systems (which depend on microfabricated surface traps and precision laser optics).
The IBM Acquisition and What It Signals
IBM’s move tells us several things at once.
First, IBM now operates a two-modality quantum strategy. Superconducting qubits remain the foundation through the Starling (2029) and Blue Jay (mid-2030s) milestones, but Gambetta told Reuters that spin qubits’ size advantage “will start to matter” at the Blue Jay timescale. That is IBM acknowledging, publicly, that superconducting qubits alone may not be the endgame. Google made a similar diversification move earlier in 2026, broadening into neutral-atom technology. The era of single-modality bets at the major labs appears to be closing.
Second, the acquisition pairs HRL’s integrated QPU architecture with IBM’s Anderon quantum foundry, announced in May 2026 with $1 billion in CHIPS Act funding and $1 billion from IBM. Anderon is a 300-mm quantum wafer fabrication facility in Albany, New York, purpose-built for superconducting qubit production. Gambetta told Reuters that HRL’s chip fabrication will shift to IBM’s New York facility. The combination of a quantum-specific 300-mm fab with HRL’s cryo-CMOS and qubit expertise puts IBM in a position to manufacture both superconducting and silicon spin qubits on the same industrial infrastructure. No other organization has that capability.
Third, the timing of the Nature paper relative to the acquisition announcement is notable. IBM signed the acquisition agreement on July 23. The Nature cover story appeared on July 29. These events were clearly coordinated. Publishing the most significant result in HRL’s history the week after the acquisition announcement maximizes IBM’s narrative: this was not a distressed acquisition of a lab facing layoffs (which Nature’s own news coverage noted HRL had experienced earlier in 2026), but a strategic investment in world-class capability. The science is real; the staging is also real.
Silicon Spin Is Having a Week
The HRL paper did not appear in isolation. The same Nature issue carried the Delft/QuTech spin-shuttling result from Undseth and colleagues. On the same day IBM announced the HRL acquisition, Hitachi, Intel Japan, and AIST launched a NEDO-funded project to develop silicon spin qubits on Intel’s 18A (1.8-nm class) process. Japan’s national quantum programs have committed over ¥150 billion to quantum technology. Diraq’s September 2025 result on industrial 300-mm wafers and Silicon Quantum Computing’s 11-qubit processor with fidelities reaching 99.99% already established momentum for the modality.
What I wrote in Quantum Systems Integration about silicon spin qubits hiding in plain sight is proving prescient. The modality was the youngest of the five I assessed, with no system deployed at the scale of superconducting or trapped-ion platforms. That is still true. But the convergence of HRL’s systems integration, Delft’s spin-shuttling connectivity, Diraq’s manufacturing validation, and IBM’s industrial commitment has compressed the timeline. Silicon spin is no longer the option with the longest time horizon. It is the option with the clearest path to semiconductor-scale manufacturing, and the field’s largest company just bet its future on it.
What This Means for PQC Migration Timelines
For readers tracking Q-Day and PQC migration urgency, this paper does not change the near-term threat assessment. HRL demonstrated seven qubits doing repetition codes. Breaking RSA-2048 with Shor’s algorithm requires on the order of 1,400 logical qubits and roughly a million physical qubits under the most optimistic current estimates (Gidney 2025). The gap is enormous.
What this paper affects is the long-term trajectory of the “engineering” portion of the CRQC timeline. If silicon spin qubits can be manufactured on industrial wafer lines with the yield curves the semiconductor industry routinely achieves, and if the cryo-CMOS controller architecture eliminates the wiring bottleneck, then the scaling path from hundreds to millions of physical qubits looks more like a semiconductor manufacturing ramp than a sequence of one-off laboratory breakthroughs. Semiconductor manufacturing ramps are predictable in a way that physics breakthroughs are not.
That does not move Q-Day to next year. It does add credibility to the thesis that quantum computing will eventually reach the scale that matters. And as I have argued before, the question of when to start PQC migration stopped being a function of Q-Day predictions years ago. Regulators, insurers, investors, and clients have already set their own quantum deadlines. The HRL result reinforces the engineering plausibility of large-scale quantum computing without changing the action that organizations need to take right now, which is the same as it has been: start migrating to post-quantum cryptography.
