Diraq Eight-Qubit Foundry Silicon Array

July 9, 2026— Researchers from UNSW Sydney, Diraq, and imec reported in Nature Communications that they tuned and coherently controlled a linear array of 8 silicon spin qubits fabricated on imec’s 300 mm CMOS pilot line in Leuven, Belgium. The paper, “Eight-qubit operation of a 300 mm SiMOS foundry-fabricated device,” led by Andreas Nickl and Tuomo Tanttu of UNSW Sydney and Diraq, with Diraq founder and CEO Andrew Dzurak among the senior authors, circulated as a preprint since December 2025.

The device is a chain of eight quantum dots defined by polysilicon gates at a 90 nm pitch on an isotopically enriched silicon epilayer carrying 400 ppm of residual ²⁹Si, with single-electron transistors (SETs) at each end for spin readout. Operating in a dilution refrigerator near 20 mK under a 0.5 T magnetic field, the team addressed each qubit individually through electron spin resonance and operated the array as four two-qubit unit cells. Each qubit’s spin-up and spin-down states are split by roughly 14 GHz under the applied field, and small differences in electron g-factors give each qubit a distinct resonance. Ramsey coherence times reached up to 41 µs (21 µs average across the eight qubits); Hahn-echo times reached up to 1.31 ms (0.7 ms average). Readout of the four central qubits used a cascaded charge-sensing protocol, in which a spin-dependent charge movement in one of the central pairs triggers a cascade of electron hops that the end SETs detect. A two-qubit controlled-phase (CZ) gate was demonstrated on one adjacent qubit pair, with low phase noise.

Set against last September’s result, the new work extends the same foundry process to an array four times larger while preserving qubit coherence; the paper, however, reports no gate-fidelity benchmarks, and a two-qubit gate was demonstrated in only one of the array’s four qubit pairs.

That earlier result set a high bar. In September 2025, largely the same UNSW–Diraq–imec team ran gate set tomography on four nominally identical two-qubit devices, of a design chosen for its estimated optimal parameters, from a single 300 mm wafer, and reported in Nature that every operation exceeded 99% fidelity, with state preparation and measurement reaching 99.95% on the best device. I covered that paper in detail at the time, and imec’s announcement framed it as the moment industrially fabricated spin qubits matched academic hero devices.

Diraq’s public roadmap targets millions of qubits by 2031, tens of millions by 2033, and a cost below one dollar per physical qubit. The company advanced to Stage B of DARPA’s Quantum Benchmarking Initiative in November 2025, took an A$20 million investment from Australia’s National Reconstruction Fund Corporation in February 2026, and in May 2026 signed a letter of intent with the U.S. Department of Commerce for up to $38 million in planned CHIPS R&D funding; in the same nine-company round, GlobalFoundries took a separate $375 million planned award for a domestic quantum foundry and announced a manufacturing partnership with Diraq.

My Analysis

The Unit-Cell Strategy, and Where the Hardware Pushed Back

The experiment’s organizing idea is decomposition. Rather than confronting an 8-qubit system as one monolithic tuning problem, the team operated the chain as four two-qubit unit cells, each a familiar object from the group’s earlier work. All 8 dots were brought up as working qubits and addressed individually, with initialization and parity readout based on Pauli spin blockade, and real-time feedback tracking the SET operating point and each qubit’s Larmor frequency. Ramsey coherence reached 41 µs on the best qubit, matching the 40.6 µs of the benchmarked two-qubit devices and, as the authors note, exceeding comparable devices from academic cleanrooms; Hahn-echo coherence reached 1.31 ms against 1.9 ms before. Phase coherence held across the exchange fingerprint maps, which the authors read as evidence of low charge noise around the qubits.

Where the hardware pushed back hardest was entanglement. Of the four qubit pairs, one showed a clean, controllable exchange interaction and supported a calibrated controlled-Z gate, with exchange turning on exponentially at a slope of 33.7 decades per volt. The two central pairs never reached exchange turn-on: an electron would tunnel away to a spurious quantum dot first. The fourth pair’s exchange switched on abruptly rather than controllably, and the paper points to dots forming underneath the barrier gates, along with lateral shifts in the electrons’ positions, as the layout problems responsible. Getting exchange to work in the good pair required loading 9 electrons into one of its dots to enlarge the electron wavefunctions enough to overlap, because the 90 nm gate pitch of this generation left the dots too far apart; configurations with as many as 13 electrons in a single dot were explored. The authors are candid about the ceiling: the result “is not a demonstration of the scalability of two-qubit gate tuning,” and entangling gates among the qubit pairs remain, by their own account, undemonstrated. A tighter pitch is the stated fix, and the same group has already posted a follow-up preprint, “Multi-Qubit Entanglement of Unit Cell Pairs in SiMOS,” that goes after exactly this gap.

One boundary needs drawing before the result gets compressed into a single number: this paper reports no gate-fidelity benchmarks. The manuscript reports no gate set tomography, randomized benchmarking, or per-gate error rates; the above-99% fidelities associated with this fabrication line belong to the September 2025 Nature paper on two-qubit unit cells, which the new work cites as prior work. What the new paper adds is the demonstration that those unit cells can be instantiated four at a time on one chip and keep their coherence. In my Diraq company profile I noted that, as of 2025, the company had not demonstrated a multi-qubit array with full control beyond two-qubit gates. The new paper closes half of that gap: the array exists, holds its coherence, and can be read out; controlled entanglement across it is the half still open.

Two Sensors for Eight Qubits: The Readout Result That Scales

The finding I consider most consequential for scaling is the readout. When the array grew from 2 qubits to 8, the sensor count did not grow with it. Two SETs at the ends of the chain read out all four qubit pairs: the lateral pairs directly, and the two central pairs through an electron-cascade technique first shown at Delft in 2021, in which the outer pairs are biased near a charge transition so that a spin-dependent charge movement in a central pair triggers a domino of electron hops outward that the end SETs pick up. The signal arrives at the sensor with better contrast than a distant SET could extract from the middle of the chain directly, and the scheme is designed to keep the total electron number in each double-dot cell constant. Related work on 300 mm silicon MOS devices has extended cascade readout to radio-frequency speeds.

Sensor fan-out is one of the failure modes that kills qubit modalities at scale, and it belongs to the engineering dimension my CRQC Quantum Capability Framework tracks as E.1: Engineering Scale and Manufacturability. A readout architecture that avoids adding a proximal sensor for every new pair, at least at this scale, is a real architectural answer to a constraint that decides whether a modality survives contact with scale. It pairs naturally with the control-side answer the same ecosystem produced last year, when Diraq and Emergence Quantum showed a milli-kelvin CMOS control chip running beside spin qubits while adding no measurable noise, with only small heating effects at its fastest clock rates. Readout that scales and control that co-locates are the two halves of the wiring problem.

The caveats deserve equal print. Cascaded readout is a calibration-sensitive, multi-step process, and this paper does not run it at the repetition rates and latencies that real-time quantum error correction demands. Connectivity is the axis the device does not touch at all: a strictly linear chain cannot implement the surface code, the authors point to bilinear and sparse two-dimensional layouts as the destinations, and qubit connectivity and routing sits as its own lane in my capability framework precisely because architectures that look clean at 8 qubits have a habit of hitting routing walls at 800. Neither two-dimensional operation nor error-correction-speed readout is shown here, and neither is claimed.

Two other numbers cut in different directions. The qubit g-factors landed within Δg = 2.17 × 10⁻³ of one another, about 0.1% in relative terms and a third of what atomistic simulations predicted for this platform, which bodes well for the global-field control schemes silicon will eventually need, since millions of individually tuned microwave lines will never fit in a refrigerator. Rabi frequencies, on the other hand, sat between 141 and 205 kHz, limited by antenna placement and by heating at higher drive power, which puts a single π/2 rotation above a microsecond and leaves room for a couple dozen such operations inside the best qubit’s 41 µs Ramsey window, and half that against the 21 µs array average.

Coherence Held at Eight Qubits. Fidelity Is the Next Test.

Coherence and fidelity get conflated constantly in quantum coverage, so let me separate them. Coherence times measure how long a qubit remembers its state while idling. Fidelity measures how accurately an operation executes under realistic control, crosstalk and calibration drift included. The new paper measured the first and maintained it across a four-times-larger device, which is meaningful evidence that imec’s low-charge-noise process holds up in longer arrays. Gate fidelity went unmeasured.

The distinction has teeth because this same team set the benchmarking standard. The September 2025 work ran gate set tomography across 12,263 circuit sequences per device to extract individual error channels, and it identified residual ²⁹Si nuclear spins as the dominant noise source, with further isotopic purification as the fix. That is the evidentiary standard the 8-qubit device has not yet met. Until an array of this size is benchmarked, ideally under simultaneous operation with crosstalk quantified, the fidelity question for foundry-fabricated arrays stays open, and it is the question the scaling thesis ultimately reports to.

For anyone mapping this to error correction, the threshold numbers frame it. Surface-code fault tolerance requires physical error rates below roughly 1%, and operating usefully below threshold requires comfortable margin; the 2025 paper itself named 99.9% across all operations as the realistic target for practical overheads. An 8-qubit chain with one working entangling pair sits several demonstrations away from that conversation, and the authors position linear arrays as a starting point for initial error correction codes at best, with the connectivity this generation lacks as the prerequisite for anything more.

Temperature is the other integration variable hiding in the methods. This experiment ran near 20 mK. Diraq’s long-term architecture co-locates CMOS control electronics with the qubits, and control electronics dissipate heat that a dilution refrigerator’s coldest stage cannot absorb at scale. The platform’s pressure valve is hot operation, which the same UNSW–Diraq lineage demonstrated above 1 K in 2024 — but hot, dense, and co-controlled have never appeared in the same device, and reconciling them is the kind of stack-level engineering problem I map in Quantum Systems Integration. This array is one corner of that map, measured cold and controlled from room temperature.

Eight Qubits Against a Million-Qubit Roadmap

Diraq’s roadmap calls for millions of qubits by 2031 and tens of millions by 2033, the year DARPA’s benchmarking program uses as its utility-scale test. Set the paper against those targets and the distance is stark: from 8 coherent qubits with one working two-qubit gate to millions of interconnected, error-corrected qubits is a jump of more than five orders of magnitude in five years, and the tens-of-millions 2033 target pushes it past six. No computing hardware, classical or quantum, has scaled at that rate on the strength of its own tooling.

Its counterargument is that it is not relying on its own tooling. The thesis, which I examined in my analysis of the Nature Reviews CMOS-compatibility assessment, is that spin qubits inherit the semiconductor industry’s fabrication base, the most refined manufacturing capability humans have built. Institutional money is treating the thesis as credible: DARPA advanced Diraq to QBI Stage B, the Commerce Department signed a letter of intent for up to $38 million, GlobalFoundries paired its $375 million quantum-foundry award with a Diraq partnership, and Australia’s sovereign fund bought in. The fabrication half of the thesis keeps getting validated, first by the 2025 fidelity paper and now by an 8-qubit array whose wafer, gate stack, and process flow came off the same industrial line.

The unvalidated half is everything between fabrication and computation, and this paper doubles as a frank inventory of it. The gate pitch needs to shrink so exchange works at low electron numbers in every pair. The architecture needs to leave one dimension. Tuning needs to stop being artisanal: the eight qubits here were tuned one by one, with no automated bring-up reported, and that mode of tuning does not stretch to a thousand, which is why Diraq has been pointing GPU-accelerated machine learning at automated calibration through its NVIDIA and Quantum Machines partnership. Benchmarked, simultaneous multi-qubit operation is the remaining entry, and the May preprint goes after it. The sub-dollar-per-qubit figure belongs on this list too: unit economics only mean something after yield, tuning time, and control overhead amortize across working devices, and 8 individually tuned qubits produce no data on any of those denominators.

For scale, the frontier elsewhere in the spin-qubit world: a 10-qubit germanium array at Delft, a 6-qubit Si/SiGe processor with universal control, and Intel’s 12-dot arrays fabricated on its own 300 mm line. My silicon spin qubit modality page tracks the field’s single-digit-to-low-double-digit counts against superconducting and neutral-atom machines running hundreds to thousands of qubits. Silicon’s wager has always been the manufacturing curve, and papers like this one are how the wager gets tested.

What This Means for CRQC Timelines

Nothing in this result moves the arrival date of a cryptanalytically relevant quantum computer, and my Q-Day estimate does not shift on it. Within my capability framework, the paper strengthens the evidence base for exactly one dimension, E.1 manufacturability, for exactly one modality. It contributes nothing to error correction, logical gates, or algorithm-level capabilities, which is where CRQC timelines are decided. Silicon’s ladder on those dimensions is being climbed in other labs; the platform recorded its first quantum error detection in January 2026 and its first universal logical operations in March 2026, both of which I track on the modality page.

Silicon spin stays on my CRQC watchlist for one specific reason. Its pitch is more concrete about scale than any other modality’s: millions of physical qubits on a single chip. Gidney’s 2025 resource estimate put RSA-2048 within reach of under a million noisy qubits, assuming 0.1% gate errors and microsecond-scale surface-code cycles. A modality that cannot yet show 10 benchmarked qubits, but that could plausibly print 10 million of them on existing fab lines in the 2030s, deserves a different kind of scrutiny than one showing 1,000 qubits today with no route past 100,000. The paper is a small, honest data point in favor of the printing half of that sentence, and silent on the rest.

What would move my assessment: benchmarked gate fidelities, via gate set tomography or equivalent, on a foundry-fabricated array of 8 or more qubits under simultaneous operation, an error-correction demonstration on foundry silicon, or a working two-dimensional array from the imec process. Those are the papers to watch from this group over the next 18 months, starting with the entanglement follow-up already on arXiv. For defenders, none of the watching changes anything operational: harvest-now-decrypt-later collection does not pause for device physics, and migration deadlines are being set by regulators, insurers, investors, and clients regardless of which qubit crosses the finish line. An 8-qubit chip in Leuven moves none of them.