Qarakal’s Pangaea Architecture Shrinks the Routing Region Tenfold, Not the Machine

August 5, 2026 – Qarakal Quantum announced Pangaea, a three-dimensional superconducting quantum computing architecture that the company says maintains fault tolerance with “1/10th of the required qubit count of traditional approaches”.

The release was accompanied by an arXiv preprint, “The Pangaea Architecture: Fault-Tolerant Heterogeneous Topological Codes via a Quantum Bus”, submitted August 3 and revised August 6. Sheir Yarkoni, Chen Scheim, Daniel Hakshuri, and Nadav Katz are the authors, with Yarkoni and Scheim listed as equal first authors. Qarakal has also published an executive summary of the paper.

Pangaea replaces the standard two-dimensional lattice-surgery routing region with what the company calls a quantum bus. The bus is an auxiliary gauge-code strip, $$d$$ qubits wide and $$\ell$$ rows long, into which logical code patches are inserted through dedicated slots. Products of local gauge-check outcomes on the bus reconstruct joint logical operators between patches that are not physically adjacent.

A length-$$\ell$$ bus connects $$N_L = \ell + 1$$ logical qubits. The mediating region therefore grows as $$O(dN_L)$$ rather than the $$O(d^2N_L)$$ a conventional two-dimensional ancilla region requires. The full layout in Figure 2 uses two orthogonal buses, one aligned to each patch’s logical $$Z$$ boundary and one to its logical $$X$$ boundary, because a measurement-based CNOT needs both parity measurements.

The tenfold figure comes from Figure 7 of the preprint, whose caption describes what it plots as “Total physical qubits for a single merge vs. code distance”. The comparison covers the routing region plus the two logical patches participating in that merge. It does not cover the remaining 48 patches of the 50-logical-qubit system, which both architectures must build and pay for identically.

The paper reports pseudo-thresholds from Stim simulations at code distances 3, 5, and 7 and bus lengths 1, 3, 5, and 7. Homogeneous surface-to-surface buses, decoded with minimum-weight perfect matching, give $$p^* = 0.43\%$$ at $$d=3$$, $$1.13\%$$ at $$d=5$$, and $$1.27\%$$ at $$d=7$$. Heterogeneous surface-to-color buses, decoded with belief propagation plus ordered-statistics decoding, give $$0.36\%$$, $$1.13\%$$, and $$1.25\%$$.

The abstract claims up to ten times fewer physical qubits. The specific 10.1x ratio appears in Figure 7 at $$d=13$$. The authors reach that point by log-linear extrapolation and label it an order-of-magnitude estimate rather than a simulated result.

The paper also builds a 15-to-1 magic-state distillation module from six logical patches. Four color-code patches hold noisy magic states, a fifth acts as ancilla, and a surface-code patch receives the distilled output, all mediated by a shared bus. Qarakal computes its space-time volume at 66 against 121 for the standard surface-code implementation.

Qarakal Quantum was founded in September 2024 according to Startup Nation Central, initially under the name Qhipu Quantum, and received an Israel Innovation Authority grant in January 2025. The company’s About page lists Nissan Maskil as CEO and Katz as CTO, with Israel Aerospace Industries and the Hebrew University of Jerusalem as supporting partners.

Katz holds a professorship at Hebrew University’s Racah Institute and completed his postdoctoral work with John Martinis, who shared the 2025 Nobel Prize in Physics with John Clarke and Michel Devoret. In April 2026 Qarakal signed a joint development agreement with Nasdaq-listed Inspira Technologies to test 3D-printed cryogenic interconnect structures at millikelvin temperatures.

Neither the preprint nor the launch material discloses a chip implementing the Pangaea bus, a bus-mediated logical operation performed on hardware, or a Pangaea-specific hardware schedule. The preprint has not been peer reviewed.

My Analysis

I reconstructed Figure 7 from the paper’s own Appendix B before writing any of this, because the gap between what the figure shows and what the release says is large enough that I wanted to be sure I hadn’t misread it.

Appendix B gives the bus qubit count exactly:

$$$n_{\text{bus}} = \frac{3d\ell + d + \ell + 1}{2}$$$

At the headline operating point, $$d = 13$$ and $$N_L = 50$$ (so $$\ell = 49$$), that comes to 987 physical qubits per bus. A rotated surface-code patch at $$d=13$$ costs $$2d^2 – 1 = 337$$ qubits including ancillas. Add two participating patches and Pangaea’s merge costs 1,661. On the two-dimensional side, an $$O(d^2N_L)$$ ancilla region plus two patches comes to roughly 17,500. The ratio is 10.6x, close enough to the paper’s 10.1x that I’m confident the reconstruction reads the plotting convention correctly.

Then I put the other 48 patches back.

The arithmetic Figure 7 leaves out

A 50-logical-qubit machine has 50 logical qubit patches in it, and we have to pay for all of them. Fifty patches at $$d=13$$ cost 16,850 physical qubits, and that bill arrives whether you route with a Pangaea bus or a conventional ancilla region. Figure 7 excludes it from both curves, which is defensible for a figure captioned for a single merge and indefensible the moment the number is described as a machine-level saving.

Counting the static footprint of both buses and all fifty patches:

The ratio is between 1.4x and 1.9x, depending on which two-dimensional layout you benchmark against. Daniel Litinski’s “A Game of Surface Codes” is the paper’s own reference [10], and its compact block is more qubit-efficient than the generic $$O(d^2N_L)$$ region Qarakal compares to. Against that layout Pangaea saves about 28 percent.

Two honest caveats on my own table. The compact block buys its density with time – up to nine logical steps to consume a magic state where the intermediate block takes five – so a static qubit count flatters it. And 18,824 is not a machine estimate either. The paper specifies no bus replication for throughput, no concurrency model for disjoint operations on a shared bus, no logical ancilla allocation, no factory count, and no decoding hardware.

What the table shows is narrower and still decisive. When the same 16,850 qubits are added to both sides of a ratio, the ratio compresses toward one, and no tile-counting convention changes that.

A tenfold reduction and a reduction of under two times have very different consequences for anyone modeling hardware timelines.

The classical computing industry went through its own version of this argument around 2001, when AMD introduced PR ratings and Apple ran the megahertz myth campaign, both attacking the habit of quoting one subsystem’s number as though it described the whole machine. Clock speed was a real measurement. It just wasn’t the measurement buyers thought they were reading.

The headline number is extrapolated past the data

Figure 7 marks three matched-error-rate ratios: 3.5x at $$p_L = 10^{-4}$$, 7.4x at $$10^{-8}$$, and 10.1x at $$10^{-12}$$. Yarkoni and colleagues say plainly that anything at distance 9 or above extends a fit and should be read as a rough magnitude rather than a simulation result.

The deeper problem is bus length, not code distance. Every point at $$N_L = 50$$ implies a bus of 49 rows. The principal simulations stop at 7, and Appendix D reaches 9, but only for distance-3 patches with two to six participating logical qubits, where the logical error rate stays inside one order of magnitude across that range.

So none of the 50-qubit points is directly simulated at that system size, including the modest 3.5x one. Every extrapolation in fault tolerance is an argument that nothing new goes wrong over the extrapolated range, and long shared buses are where something new might – correlated faults along the strip, crosstalk between adjacent slots, and the accumulated chance of a fault entering somewhere across 49 rows of gauge checks.

The two-dimensional curve is modeled rather than simulated as well. The authors assume matched error behavior along the merge boundary and treat total logical error as a combinatorial function of ancilla footprint. Neither side of the comparison is assumption-free.

Two smaller items make the reported numbers friendly – resets and the final destructive readout are treated as ideal, and the $$M_{ZZ}$$ results are inferred from the simulated $$M_{XX}$$ circuits by exchanging observables rather than simulated separately. Both are conventional in this literature, though the first is directionally optimistic and the second is better described as untested against hardware asymmetry.

Qarakal derived a better number and didn’t promote it

Section IV contains the finding I would have led the release with.

The heterogeneous distillation module absorbs the measurement-dependent Clifford byproduct into the destructive readout of the reusable color-code patch, conditioned on the decoded bus parity, which means the adaptive correction needs neither an extra protected logical patch nor a further bus-mediated surgery step. Persistent area works out to roughly 6 tiles against 11 for the standard surface-code factory. Time is a wash at 11 logical steps each. Space-time volume comes to 66 against 121, a factor of 1.8.

The factor of 1.8 is a high-distance asymptote. The area of 6 tiles drops the bus contribution of $$5/d$$, which at the $$d=13$$ operating point used elsewhere in the paper gives 6.4 tiles, a volume of 70, and a factor of 1.7. Either way it is a calculation rather than a fit, which is more than the 10.1x can claim.

It is also a module-level space-time estimate that excludes the cost of preparing the raw color-code magic states, the module’s rejection probability, and the output fidelity under the bus noise model. Magic-state production is the dominant cost in most surface-code and Clifford-plus-T architectures, and shaving it by a third to a half changes the factory budget on any machine that needs T gates in bulk.

It went out on the wire as one tenth. The number that survived the trip came from an extrapolation; the number that came from a complete calculation stayed in Section IV.

The heterogeneous interface has no demonstrated real-time decoder

The genuinely new contribution is the surface-to-color interface. Yarkoni and colleagues show how to expose a color-code patch’s logical operator as a rough boundary that slots into the same bus as a surface-code patch, extending weight-4 stabilizers to weight-6 the way surface-code weight-2 stabilizers extend to weight-4. Appendix E works through the subsystem-code bookkeeping and demonstrates that the merged code carries parameters $$[[n_{\text{merge}}, N_L – 1, \mu(d-1)/2, d]]$$ with no unconstrained logical degrees of freedom left over. That is careful work and it is the part of the paper I would keep.

The catch is in the decoding, where the surface-to-surface circuits use minimum-weight perfect matching. The authors decoded the surface-to-color circuits with belief propagation plus ordered-statistics post-processing at OSD order 10, combination-sweep method, 20 iterations, parallel schedule. They report that weaker settings made the logical error rate stop behaving monotonically at distance 5, which they resolved by raising the OSD order and switching schedules. That is honest reporting and also a small signal about how sensitive the heterogeneous result is to decoder configuration.

What the paper does not report is any decoder latency, throughput, memory footprint, or hardware implementation. High-order BPOSD with combination sweep is computationally heavy and no real-time implementation of it has been demonstrated, so the result establishes decoder accuracy in offline simulation and leaves real-time feasibility open.

Progress here can be fast. IBM reported real-time qLDPC decoding under 480 nanoseconds in November 2025 using a purpose-built FPGA implementation of Relay-BP on the gross code, which is neither BPOSD nor Pangaea’s merged surface-color code, but does show how quickly this particular gap can close. For now the architecture’s most distinctive capability depends on a classical component nobody has built, and that dependency is Capability D.2, decoder performance, in my CRQC Quantum Capability Framework.

The three-dimensional physical layout carries its own bill. Qarakal means physically stacked layers with high-yield inter-layer couplers, and names flip-chip integration, through-silicon vias, and modular chip-to-chip couplers as candidates. Their Outlook paragraph on fabrication variability and correlated noise is more candid than most company preprints manage. It also describes Capability E.1 work that has not been demonstrated for Pangaea.

Pangaea against the qLDPC route

Qarakal’s positioning against high-rate codes is legitimate, and the trade it names is real. qLDPC architectures buy encoding rate by demanding long-range physical connectivity. Pangaea keeps nearest-neighbor connectivity with degree-6 couplers throughout, moving the routing burden into a stacked geometry instead.

IBM’s Loon processor takes the opposite bet on the same problem, adding on-chip c-couplers that reach past nearest neighbors to give the gross code the connectivity it needs. Both are trying to relieve the same logical-routing constraint, and each buys its relief with a different fabrication problem – Pangaea with inter-layer coupling and vertical yield, IBM with long low-loss couplers and multilayer routing.

The comparison the paper does not make is the quantitative one. Theodore Yoder, Michael Beverland and colleagues at IBM claim an order of magnitude more logical circuit per physical qubit in Tour de Gross (arXiv:2506.03094). Paul Webster and the Iceberg Quantum team put RSA-2048 under 100,000 physical qubits with generalized bicycle codes in the Pinnacle architecture (arXiv:2602.11457). Both sit in Pangaea’s bibliography, and neither appears in a table beside it.

In fairness, they are different objects, since Tour de Gross is an end-to-end universal architecture and Pinnacle is a workload-level cryptanalytic estimate, so the reasonable ask is not a single table but a normalized comparison at matched workload, noise, and failure budget. Pangaea offers none.

Then there is reference [8]. Boren Gu and co-authors published “Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid” in June 2026, using nearest-neighbor iSWAP walks to get high-rate qLDPC memories onto a planar grid with no long-range hardware graph at all. Their introduction singles out vertical routing through the processor stack as the alternative it is avoiding, on the grounds that three-dimensional integration brings substantial fabrication complexity.

That is a direct challenge to Pangaea’s central premise, published six weeks earlier, arguing the opposite trade. Gu and colleagues demonstrate memories rather than the long-range logical operations and cross-code interface Pangaea provides, so it isn’t a replacement. It does make “high-rate qLDPC needs long-range couplers” an unsafe generalization. Qarakal cites the paper twice, once in the introduction and once in the Outlook as future work, without engaging with the argument.

What this changes for CRQC timelines

Nothing.

Architecture papers can move CRQC estimates when they deliver credible end-to-end resource models for a cryptographic workload. That is why Craig Gidney’s under-a-million-qubit RSA-2048 estimate and Madelyn Cain and colleagues’ 10,000 reconfigurable atoms for Shor’s algorithm reshuffled the picture in 2025 and 2026.

Pangaea doesn’t do that. It models a logical interaction primitive and one distillation module – no complete processor, no workload, no runtime, no decoder. A saving of under two times in static qubit count at fixed logical error rate doesn’t move a Q-Day estimate, and nothing here should change a migration deadline.

What it does tell us is how to read the next twelve months of announcements. Every architecture group is now claiming an order of magnitude over the planar surface code. IBM claims it, Iceberg claims it, and Qarakal claims it.

The trouble is that “the surface code” is not one baseline: layout, routing allocation, throughput, code distance, noise model, and workload all move the denominator, and the most expensive plausible choice makes the best headline. When a vendor claims a tenfold win over the surface code, the questions we should be asking are which layout, counting which qubits, at which simulated distance, and how it compares to the bicycle codes.

There is a version of the quantum panic industry problem that runs in the opposite direction from the one I usually write about. Instead of inflating the threat, it inflates progress, and the mechanism is the same: a real technical result, correctly scoped in one place, restated one abstraction level too high somewhere downstream.

Here the scope widens in three steps. Figure 7’s caption measures one merge and says so. The abstract drops the single-merge qualifier and states the tenfold figure at the 50-logical-qubit scale, hedged only by an upper-bound phrase. The release turns that into fault tolerance at one tenth the qubit count, and adds claims about wiring, control complexity, and energy consumption the preprint never models.

Maskil then says on the record that reaching the same fault-tolerant capability with a tenth the physical qubits makes the machine simpler to build and control. That is the machine-level claim, made by a named co-founder, not something that happened to a number in transit.

I want to be clear about who the criticism is aimed at. Yarkoni, Scheim, Hakshuri and Katz wrote a careful paper with an unusually honest limitations section, a novel cross-code surgery primitive, and a distillation construction that stands on its own. They captioned Figure 7 accurately and labeled their extrapolations as extrapolations. The widening starts in their own abstract, and I would rather say that than tell a tidier story in which the physicists are blameless and an anonymous comms team did it.

Coverage in the two days after the announcement did not help. The Quantum Insider, Quantum Computing Report, Quantum Zeitgeist, and TechTimes all reproduced the tenfold figure. TechTimes opened by calling it a peer-reviewed architecture paper before correctly identifying it as a preprint two sentences later. Quantum Computing Report went furthest into the technical content, describing the gauge-code strip, the pseudo-threshold simulations, and the distillation module. None of them mentioned that the figure counts a single merge.

The interesting engineering is in Section IV and Appendix E. The number everybody quoted is in a figure whose caption says what it counts.