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August 3, 2026 — Researchers from the California Institute of Technology and Oratomic have introduced mitten codes, a family of quantum low-density parity-check (qLDPC) codes built from non-abelian group algebras. The codes have a 20% encoding rate and check weight 9. The largest reported candidate encodes 195 logical qubits in a 975-data-qubit block and is written [[975, 195, ≤24]] because its minimum distance is estimated rather than exactly certified. The preprint was submitted to arXiv on July 30, 2026.
Mitten codes are qLDPC codes with instances ranging from a compact [[150, 30, 10]] through [[540, 108, 18]] to the [[975, 195, ≤24]] candidate. Their name comes from the block structure of their check matrices: four similar “fingers” and a distinguished “thumb.” In the authors’ 0.4%-error memory benchmark, the 975-data-qubit [[975, 195, ≤24]] block achieved a lower logical error rate than a 112,320-data-qubit stack of 195 distance-24 rotated surface-code patches decoded with minimum-weight perfect matching. The 115x data-qubit-count ratio is real, but it compares data-qubit block sizes rather than complete processor footprints, and the two systems used different decoders.
The bottom line: at 0.1% physical error rate, the team observed two logical failures across 15 billion independently simulated $$\bar{X}\bar{X}$$ surgery quops on the [[540, 108, 18]] code. The result is statistically consistent with an expected processing capacity of order 10 billion quops (the paper’s own instruction-set-dependent metric for reliable operations before the first error), but it is not a zero-error 10-billion-operation computation.
The research team includes Aditya Bhardwaj, Muzhou Ma, and Nadine Meister from Caltech alongside Robbie King, Dolev Bluvstein, Madelyn Cain, and Qian Xu from Oratomic. John Preskill and Hsin-Yuan Huang hold dual affiliations at both institutions. Six of the nine authors carry Oratomic affiliations. Several of these researchers are also authors of the March 2026 paper “Shor’s algorithm is possible with as few as 10,000 reconfigurable atomic qubits.” The mitten codes paper notes that the same processor discovery pipeline produced some of the quasi-cyclic lifted product codes used in that earlier analysis.
The paper introduces three instruction sets for universal fault-tolerant quantum computation on mitten codes, a novel “telescoping decoder” that matches or outperforms current state-of-the-art decoders, modeled hardware designs for both neutral atom and superconducting platforms, and sQetch, a GPU-based code distance estimator that runs up to 800,000 times faster than existing methods. The authors have released sQetch, the code-search toolkit, processor-code and gadget files, superconducting layouts, and neutral-atom syndrome-extraction animations under an MIT licence. The telescoping decoder itself is not yet included in the repository.
The paper acknowledges concurrent work by Yifan Hong, who independently developed non-abelian lifted product codes with the same 1/5 encoding rate, and by Han Zheng, Guo Zheng, Liang Jiang, and Qian Xu, who constructed highly symmetric logical bases and efficient logic for abelian lifted product codes. Both concurrent papers were submitted to arXiv on July 30.
My Analysis
The Non-Abelian Breakthrough That Makes This Possible
The technical core of this paper is a mathematical result that will not make headlines but should: using non-abelian groups to construct lifted product codes removes a distance obstruction that constrains abelian constructions at the same base-matrix shape and weight.
For the paper’s 1×2, weight-six base-matrix construction, using an abelian group algebra creates an unavoidable logical operator whose weight cannot exceed the classical base-code check weight, capping the code distance at 6. Non-abelian multiplication removes that particular obstruction. It does not guarantee high distance by itself, but it opens a search space in which the authors found exact-distance instances through [[540, 108, 18]] and larger candidates reported as [[630, 126, ≤20]], [[780, 156, ≤22]], and [[975, 195, ≤24]].
The group together with the selected base matrices determines the code’s parameters, its logical operator weights, its hardware layout, and its syndrome extraction schedule. The specific groups read like a catalog of finite group theory: $$C_5 \times S_3$$, $$C_4 \times D_{10}$$, $$C_9 \rtimes C_{12}$$, $$C_{13} \rtimes C_{15}$$. The [[975, 195, ≤24]] candidate is built over the semidirect product $$C_{13} \rtimes C_{15}$$ of order 195 (with a specific conjugation action defined in the paper’s Table VII). Its canonical logical $$X$$ and $$Z$$ representatives have weights 102 and 92, while its minimum distance is estimated at no more than 24 rather than proved to equal 24.
The encoding-rate comparison against IBM’s bivariate bicycle codes is stark. The [[144, 12, 12]] gross code that anchors IBM’s “Tour de Gross” architecture achieves an 8% encoding rate. The [[288, 12, 18]] two-gross code manages about 4%. Mitten codes guarantee 20% by construction, at any group size.
Five Reusable Gadgets for Clifford Processing
High encoding rate is necessary but not sufficient. A code that stores information efficiently but cannot process it is a quantum hard drive, not a quantum processor. The mitten codes paper addresses this head-on with what may be its most elegant result: the entire basic instruction set for universal Clifford processing requires only five reusable surgery gadget designs, all derived from just two seed gadgets.
This economy comes from the canonical logical basis the team constructs. Every mitten code encodes $$|G|$$ logical qubits (one per group element), and the group action maps any logical operator to any other. The $$\bar{X}$$ operators form a single orbit under left multiplication; the $$\bar{Z}$$ operators form a single orbit under right multiplication. A seed gadget that measures $$\bar{X}_e$$ (the identity-element representative) can therefore measure any $$\bar{X}_g$$ simply by rewiring its interface according to the group action. Bridging the two seed gadgets produces the remaining three measurement types ($$\bar{X}\bar{X}$$, $$\bar{Z}\bar{Z}$$, and $$\bar{Y}$$).
For comparison, a generic qLDPC code with $$k$$ logical qubits and no exploitable symmetry would need $$3k + k(k-1)$$ distinct gadgets to support the same instruction set. For the [[975, 195, ≤24]] code, that would be 38,415 gadgets. Mitten codes need five reusable gadget designs.
The paper goes further. Beyond this basic Clifford instruction set, the team constructs high-rate (“parallel”) surgery gadgets that measure up to $$k/2$$ disjoint weight-two logical Pauli products simultaneously, covering all logical qubits in one parallel surgery operation implemented over $$O(d)$$ syndrome-extraction rounds. They also construct and prove distance-preserving a protocol for parallel magic-state injection that teleports $$|G|$$ magic states into a mitten code block simultaneously, with a time overhead of $$\Theta(d_{\text{rep}})$$ independent of the number of logical qubits. Universal quantum computation requires these non-Clifford resources in addition to the five Clifford gadgets. They also build full extractors, single fixed gadgets with software-selectable activation patterns that can measure arbitrary logical Pauli products. The overheads are reported explicitly: for the [[300, 60, 14]] code, the full extractor adds 780 ancilla qubits and keeps the merged check weight at 13.
The Numbers That Matter: Processing Capacity
The paper defines “processing capacity” as the expected number of quantum operations (quops) a processor can execute before its first logical error. A quop is the paper’s own instruction-set-dependent metric: a primitive instruction counts as one quop, and parallel execution of $$m$$ primitives counts as $$m$$ quops. Cross-architecture comparisons using this metric require care, since different instruction sets count operations differently.
The headline numbers, simulated under circuit-level depolarizing noise:
At 0.1% physical error rate, the [[300, 60, 14]] code achieved a block logical error rate of approximately $$9.5 \times 10^{-12}$$ per syndrome extraction round. That corresponds to one logical error observed across over 100 billion syndrome extraction rounds. In the surgery experiments at the same error rate, the [[300, 60, 14]] code ran one billion $$\bar{X}\bar{X}$$ operations with two logical errors, and its high-rate surgery gadget measured ten $$\bar{X}\bar{X}$$ products in parallel across one billion operations with zero failures.
The [[540, 108, 18]] code pushed further: 15 billion independently simulated $$\bar{X}\bar{X}$$ surgery quops produced exactly two logical errors. Both were timelike errors in the measured operator itself, suggesting that simply increasing the number of syndrome extraction rounds would suppress them further. The observed error rate ($$1.33 \times 10^{-10}$$ per quop) is consistent with a processing capacity of order 10 billion quops.
At 0.4% physical error rate, the [[975, 195, ≤24]] code reached a block logical error rate of approximately $$4.2 \times 10^{-8}$$ per round. A 112,320-data-qubit stack of 195 distance-24 rotated surface-code patches, decoded with minimum-weight perfect matching, achieved $$2.44 \times 10^{-6}$$ at the same error rate. The mitten code outperforms by nearly two orders of magnitude while using 115 times fewer data qubits. (The comparison uses different decoders and different code architectures; it demonstrates the encoding-rate advantage rather than a controlled decoder-vs-decoder test.)
I want to be precise about what these numbers are and are not. They are simulation results under a specific noise model (uniform depolarizing, no idling noise), decoded by a specific decoder (the team’s own telescoping decoder), on codes the team designed and selected through their own pipeline. They are not hardware demonstrations. No mitten code has been built on any physical platform. The noise model does not include atom loss, a significant error source in neutral-atom hardware that the authors explicitly acknowledge. Independent replication by other groups, with different decoders and more realistic noise models, will be needed to confirm these performance claims.
The Telescoping Decoder
The decoder is itself a contribution worth separate attention. The team’s telescoping decoder is a multi-stage pipeline: two GPU-based stages running custom CUDA kernels for belief propagation (BP) and Relay-BP, followed by CPU-based serial BP stages, with integer programming via Gurobi as the final backstop. At each stage, shots that converge are resolved; only the residual of harder shots passes to the next, more expensive stage.
Benchmarked on memory experiments with IBM’s [[144, 12, 12]] gross code using the same detector error models from the Relay-BP paper, the telescoping decoder achieved a logical error rate per round per logical qubit of approximately $$6.7 \times 10^{-11}$$ at 0.1% physical error rate. This matches or improves upon all current state-of-the-art decoders tested on the same benchmark, including Tesseract (a search-based decoder), Cascade (a neural decoder), Relay-BP, and BP+OSD.
It does this at nearly double the throughput of the closest neural decoder, processing over 160,000 syndrome extraction cycles per second on a single NVIDIA H100 GPU (with a CPU core handling the rare harder shots in parallel). The team estimates that the BP stages, extrapolated to existing FPGA implementations, would achieve sub-millisecond average decoding latency on representative mitten codes assuming a 1 ms syndrome extraction cycle. That estimate is an extrapolation, not a demonstrated end-to-end real-time decoder, but the staged architecture is designed with FPGA portability in mind.
Unlike neural decoders, the BP-based stack requires no model training. The demonstrated implementation still relies on GPU and CPU processing; the real-time estimates assume FPGA implementations of the BP stages.
Hardware Mappings
The paper develops concrete hardware mappings, movement schedules, and modeled implementation estimates for both neutral atom arrays and superconducting qubit platforms. No mitten code has been implemented on either.
On neutral atoms, the group structure of mitten codes maps naturally onto atom transport via acousto-optic deflectors (AODs). For groups that decompose as direct products $$G = G_1 \times G_2$$, atoms in each block are arranged on a 2D grid with the subgroups along the axes. Group multiplication then reduces to separable row and column permutations, precisely the operations AODs can perform. Semidirect products require column-dependent row shifts, which are more complex but still structured enough for efficient transport.
The estimated syndrome extraction cycle times range from about 5 ms (smallest code, 4 AOD pairs) to about 23 ms (largest code, 2 AOD pairs). These are competitive with the cycle times reported by Zhao et al. for their ultra-high-rate codes on the same hardware model. The paper also considers a futuristic architecture with independently controlled atom trajectories (fast SLMs), which would reduce cycle times to 3-5 ms across the family.
On superconducting hardware, the team proves that every mitten code has Tanner graph thickness exactly 3 (one layer more than the bivariate bicycle codes’ thickness of 2). Using the HAL placement-and-routing algorithm developed at MIT, they achieve modeled hardware complexities ranging from 2.02 for the smallest code to 3.95 for the largest. For comparison, the [[144, 12, 12]] gross code achieves 2.12 and the [[288, 12, 18]] two-gross code achieves 2.24. The smaller mitten codes are within range of IBM’s codes on this metric while encoding substantially more logical qubits.
The Pipeline Behind the Codes
The mitten codes were not found by hand. They are the output of an automated processor discovery pipeline whose most important component is sQetch, a new GPU-based code distance estimator. The speedup is extraordinary: on the workload relevant to the pipeline (screening roughly 10 million candidate codes with 100,000 distance-estimation trials each), sQetch running on a single NVIDIA RTX 5090 completes in under a week what the previous state-of-the-art CPU estimator, QDistRnd, would require years to millennia to finish. The reported speedups range from 7,900x at ~100-qubit codes to 830,000x at ~2,000-qubit codes.
This speedup is what makes the pipeline practical. Good qLDPC codes are extremely sparse in their design spaces: only a fraction between $$10^{-5}$$ and $$10^{-3}$$ of candidates that survive cheap classical prefilters have useful distance. The pipeline narrows the search through three levels: algebraic bounds that rule out candidates without constructing the quantum code, sQetch-based distance estimation on survivors, and full circuit-level simulation with the telescoping decoder on the final candidates. Feedback loops allow codes that fail downstream validation to trigger retuning of the group or base matrices upstream.
The pipeline is general. The paper notes that the same pipeline produced some of the quasi-cyclic lifted product codes reported in Cain et al.’s “Shor’s algorithm with 10,000 qubits” paper, as well as other abelian lifted product codes described in the appendices. The direct technical connection to the earlier Shor resource estimate is this broader pipeline, not the mitten code family itself. Because every design requirement enters as an adjustable input, the pipeline can be re-run for different hardware platforms, rate targets, and instruction sets.
The qLDPC Competition
The mitten codes paper lands in a rapidly intensifying competition among qLDPC code families. Over the past two years, qLDPC codes have moved from a largely theoretical alternative to a serious challenger to surface-code-centric architectures, and the question is now which qLDPC family best serves different hardware platforms and computational targets.
IBM’s bivariate bicycle codes have the advantage of maturity. The [[144, 12, 12]] gross code has been extensively benchmarked, IBM has built the “Tour de Gross” architecture around it, and FPGA-based real-time decoders already exist for it. But the encoding rates (4-8%) are modest, and the codes encode only 12 logical qubits per block. Scaling requires tiling many blocks with inter-block operations.
Zhao et al.’s ultra-high-rate codes (QuEra/Harvard/MIT, April 2026) exceed a 50% encoding rate. Their [[1152, 580, ≤12]] candidate reached approximately $$2.9 \times 10^{-11}$$ logical errors per logical qubit per round, while the larger [[2304, 1156, ≤14]] candidate reached approximately $$1.3 \times 10^{-13}$$ and approached the teraquop memory regime. That work focused on memory and syndrome extraction rather than a complete universal logical instruction set.
Kasai codes achieve similarly high rates through a different construction (affine permutation matrices). Zhao et al.’s work builds on Kasai’s construction.
Mitten codes combine a 20%-rate non-abelian construction with directly simulated surgery operations, a high-throughput decoder stack, explicit neutral-atom movement schedules, and multilayer superconducting layouts. That integrated processor-level treatment, not the existence of logical gadgets alone, is the paper’s main differentiator. Hong’s concurrent paper and the Zheng et al. framework both make related claims about reusable surgeries and logical instruction sets for lifted product codes, so this space is moving fast.
The Oratomic Context
Six of the paper’s nine authors list Oratomic affiliations, including Preskill and Huang with dual Caltech appointments. Oratomic launched publicly on March 31, 2026 alongside the “10,000 qubits” paper and announced a 300 million USD Series A in July 2026. The company aims to build a utility-scale fault-tolerant system by 2030.
The commercial context and incentives are worth noting, not because they invalidate the work (academic-startup collaborations produce some of the field’s best research, and the tools are open-sourced), but because they shape what the paper optimizes for. The paper’s emphasis on neutral-atom hardware compatibility, the detailed AOD transport schedules, and the structured group decompositions that map onto reconfigurable atom arrays all reflect Oratomic’s hardware-specific development path.
What This Means for CRQC Forecasting
In the context of my CRQC Quantum Capability Framework, the mitten codes paper advances several capabilities as simulation results.
For B.1 — Quantum Error Correction: the paper proves the removal of a specific abelian distance obstruction and reports exact finite-distance instances through [[540, 108, 18]] along with larger estimated-distance candidates. A new 20%-rate code family with a complete logical instruction set expands the design space for fault-tolerant architectures.
For B.3 — Below-Threshold Operation: the paper provides numerical evidence consistent with an effective finite-size threshold near 0.7% under its chosen circuit-level noise model. This is useful architectural evidence, but it is not a hardware demonstration of below-threshold operation. The authors themselves note this crossing should be understood as an effective, finite-size threshold rather than an asymptotic one.
For D.2 — Decoder Performance: the telescoping decoder’s competitive accuracy and the sub-millisecond average latency extrapolation address the decoder bottleneck I have highlighted as an underappreciated engineering constraint on CRQC development. The real-time result remains an extrapolation rather than an achieved milestone.
For E.1 — Engineering Scale and Manufacturability: the superconducting hardware complexity metrics (2.02-3.95) and the neutral-atom SE cycle times (5-24 ms) provide concrete modeled estimates for mitten code processor designs on real hardware platforms. These are evidence of modeled implementability, not fabrication feasibility or manufacturing yield.
The paper matters to CRQC forecasting because it shows that quantum-error-correction overhead remains algorithmically compressible. That widens the uncertainty around long-term resource estimates. It does not, without hardware validation and an end-to-end cryptanalytic resource analysis, justify moving a Q-Day estimate forward by a decade. The bare 20% code rate (5 data qubits per logical qubit) excludes check ancillas, surgery ancillas, extractors, and magic-state factories. The paper’s own parallel magic-injection table shows that a full 195-logical-qubit processor with $$d_{\text{rep}}=7$$ magic states involves 22,815 total qubits. That ratio is still an order of magnitude better than surface codes, but the 5:1 number alone is not a system-level CRQC estimate.
For organizations evaluating their PQC migration timelines, the message remains unchanged: the deadlines are already set by regulators, insurers, investors, and clients. Whether the enabling qLDPC architecture turns out to be mitten codes, Kasai codes, bicycle codes, or something not yet invented, the migration clock is ticking.
The paper is available at arXiv:2607.28795. The code and tools are at github.com/a7b/yarn.
