IonQ Demonstrates qLDPC Breakeven on Trapped Ions — and the Flexibility Argument Just Got Harder to Ignore

June 5, 2026 – IonQ researchers published a preprint demonstrating breakeven quantum error correction with quantum low-density parity-check (qLDPC) codes on a trapped-ion quantum computer. The experiment used a stationary chain of 40 barium-133 ions to implement nine distinct error-correcting codes spanning three code families (five qLDPC codes, two topological toric codes, and a concatenated code) on a single device without any hardware reconfiguration.

The headline numbers: on a BB5 [[18,4,3]] code encoding 4 logical qubits into 18 physical qubits, IonQ achieved logical error rates 4× lower for X errors and 9× lower for Z errors compared to the only prior experimental qLDPC demonstration on superconducting hardware, the Wang et al. experiment on the Kunlun processor published in Nature Physics earlier this year. That experiment used a purpose-built 32-qubit superconducting chip with custom long-range “air-bridge” couplers designed for a single specific bivariate bicycle (BB) code, and reported logical error rates of approximately 9% per logical qubit per syndrome cycle. IonQ’s best-performing qLDPC code, a GB4 [[26,2,5]], achieved 0.96% per logical qubit per cycle for Z eigenstates.

Several code instances reached or marginally exceeded breakeven — the point where the error-corrected logical qubit outlives the physical qubits it is built from. The GB4 [[26,2,5]] code exhibited a logical qubit lifetime of 3.95 ± 0.68 seconds, compared to a physical qubit coherence time (T₂*) of 1.1 ± 0.3 seconds and a derived physical qubit lifetime of 3.3 ± 0.9 seconds. The BB5 [[24,4,4]] code similarly reached 3.36 ± 0.57 seconds.

The experiments relied on a novel implementation of the optical-metastable-ground (OMG) architecture for mid-circuit measurement and reset. This is the first time the full OMG architecture has been demonstrated in a functioning trapped-ion quantum computer. Prior demonstrations had been limited to one or two ions. The OMG approach allows ancilla qubits (the qubits measured repeatedly during error correction) to double as sympathetic coolant ions for the chain. This eliminates the need for dedicated coolant ions or a separate atomic species, resources that consume up to 50% of the ion count in other trapped-ion systems.

The paper lists eleven authors from IonQ, including Nicolas Delfosse, who also co-authored the beam search decoder used in these experiments and IonQ’s recent Walking Cat fault-tolerant architecture paper.

My Analysis

The Flexibility Story Is the Lead

The 9× improvement over the superconducting comparison is a clean result and will rightly draw attention. But the more consequential finding in this paper is the flexibility demonstration.

To implement a single qLDPC code instance on their Kunlun chip, Wang et al. had to fabricate bespoke air-bridge structures alongside Josephson junctions with carefully optimized resistances — custom hardware for one code. IonQ ran five different qLDPC codes from two distinct code families (BB5 and GB4), two toric codes, and a concatenated [[16,4,4]] code on the same 40-ion chain. The controlled-Pauli gate patterns required by these codes vary enormously (the Tanner graphs in the paper’s Figure 1C make this visually obvious), yet IonQ ran them all without changing hardware, recalibrating, or redesigning the chip.

This matters because the field is in the middle of a code design revolution. In the past year, the theoretical proposals for qubit-efficient fault-tolerant architectures have proliferated: Iceberg Quantum’s Pinnacle architecture (BB codes, February 2026), IonQ’s own Walking Cat blueprint (generalized bicycle and cyclic hypergraph product codes, April 2026), IBM’s Tour de Gross (bivariate bicycle codes, June 2025), and the Oratomic/Caltech proposal for Shor’s algorithm with 10,000 neutral atoms (March 2026). Each proposal uses different code constructions, different parameters, different connectivity requirements.

A hardware platform that can iterate across code families without physical redesign has a structural advantage in this environment. The optimal code for a given application, error model, or target logical error rate may not be the code you started with. Superconducting platforms that hard-wire connectivity for a specific code family accept a tradeoff: optimized performance for that code, at the cost of inflexibility when the best code turns out to be a different one. Trapped ions, with their all-to-all connectivity through steerable laser beams, avoid that tradeoff. The IonQ paper goes further — using optimized qubit-to-ion mappings that assign high-fidelity ion pairs to the most-used gates in each code’s syndrome circuit, squeezing additional performance (30–50% infidelity reduction) from the same hardware through software optimization alone.

I want to be precise about the scope of this advantage. It applies at the 40-qubit scale. Whether all-to-all laser-addressed connectivity remains practical at 1,000 or 10,000 ions is a different question, and IonQ’s own Walking Cat architecture acknowledges this by proposing QCCD-style ion transport for scale. The flexibility demonstrated here is real but scale-bounded.

qLDPC Breakeven Is a Different Milestone from Surface Code Breakeven

Google’s Willow experiment (Nature, December 2024) demonstrated below-breakeven performance with the surface code, producing a logical qubit whose lifetime exceeded its best physical qubit by a factor of 2.4×. That was a landmark result. But the surface code is qubit-expensive: encoding a single logical qubit at the distance needed for practical computation requires hundreds to thousands of physical qubits.

qLDPC codes exist precisely to fix that problem. They encode multiple logical qubits per code block at a fraction of the overhead. The BB5 [[18,4,3]] code encodes 4 logical qubits in 18 physical qubits. A comparable surface code protecting 4 logical qubits at distance 3 would need 4 × 17 = 68 physical qubits, nearly 4× more. At higher distances, the gap only grows.

Every major fault-tolerant architecture published in 2025–2026 depends on qLDPC codes delivering on their theoretical promise. The Pinnacle architecture claims RSA-2048 can be broken with fewer than 100,000 physical qubits, but only if qLDPC codes work as advertised in hardware. Google’s own Babbush paper proposes breaking ECC in ~4,000 logical qubits and still requires efficient logical-qubit encoding. Reaching breakeven with qLDPC codes, even at small scale, is the first experimental evidence that the encoding efficiency these architectures assume is physically achievable. That’s the “so what” of this paper. It doesn’t change resource estimates directly. It validates a foundational assumption that resource estimates depend on.

The word “breakeven” deserves some precision here. The IonQ result shows logical qubit lifetimes comparable to physical qubit lifetimes, with the GB4 [[26,2,5]] code marginally exceeding it (3.95 ± 0.68 s vs. 3.3 ± 0.9 s). The error bars overlap. Google’s Willow result was stronger in absolute terms: a 2.4× lifetime extension with exponential suppression demonstrated across three code distances. IonQ has not yet shown exponential suppression with increasing distance for their qLDPC codes — the data shows that larger codes (BB5 [[30,4,5]]) actually perform worse than smaller ones (BB5 [[18,4,3]]), because the additional syndrome rounds introduce more noise through mid-circuit measurements. Below-threshold scaling for qLDPC codes on this platform remains to be demonstrated.

The OMG Architecture: Solving the Coolant Ion Problem

The OMG (optical-metastable-ground) architecture eliminates dedicated coolant ions from the trapped-ion error correction workflow. That has direct implications for how trapped-ion systems scale.

In Quantinuum’s QCCD systems, currently the state of the art for trapped-ion quantum computing, up to 50% of the ions in the trap serve exclusively as coolant, absorbing vibrational energy generated by ion transport and gate operations. They never carry quantum information. The IonQ OMG approach instead shelves data qubits into a metastable electronic state (the 5²D₅/₂ manifold of barium) during mid-circuit measurement, then uses the ancilla qubits that are being measured to simultaneously cool the chain’s motional modes. Same ions, dual purpose.

The practical significance: the 40-ion chain in this experiment dedicated all ions to computation (data qubits + ancilla qubits), with cooling happening as a side-effect of the measurement protocol. The BB5 [[30,4,5]] code used all 40 ions (30 for the code block, 10 as ancillae), leaving zero ions idle. In a QCCD system with 50% coolant overhead, that same experiment would require 80 ions.

Two cautions. First, this is a stationary-chain architecture, not QCCD. The ions do not move. All-to-all connectivity comes from steerable laser beams that can address any pair of ions. This sidesteps the transport noise and latency that QCCD systems must budget for, but it also imposes different scaling constraints (beam crosstalk, chain mode structure). Second, IonQ’s own Walking Cat architecture proposes QCCD-style transport for scale, which means the OMG approach demonstrated here may need to be adapted for the company’s future hardware. Whether OMG-based mid-circuit measurement integrates cleanly with transport-based architectures is an open engineering question.

The Post-Selection Problem

The paper addresses this honestly, but it deserves emphasis: post-selection rates are high, especially for the larger codes. The BB5 [[30,4,5]] code rejected 74.8% of measurement shots at 6 syndrome rounds. Three out of four experimental runs were thrown away because leakage was detected during mid-circuit measurement.

The authors simulate what would happen if leaked qubits were re-initialized (erasure conversion) rather than rejected. The worst-case degradation is modest: 11% increase in logical error rate for BB5 codes, 20% for GB4 codes. These numbers suggest the post-selection is conservative rather than concealing a fragile result. But a 75% rejection rate is not compatible with operational error correction. At scale, you need every shot to count.

The dominant leakage source is technical imperfections in the OMG mid-circuit measurement protocol. This is IonQ’s first full-scale deployment of the architecture, and the leakage rate per MCM round (1.7 × 10⁻³) will presumably improve with engineering maturity. The paper frames this correctly as a current limitation with a clear path forward, not a fundamental barrier. I agree with that assessment, but I’ll note that “clear path forward” is not “demonstrated at scale,” and the distance between those two statements is where most quantum engineering programs stall.

Competitive Landscape: Where This Sits

The qLDPC experimental picture as of June 2026:

Superconducting (Wang et al., Nature Physics 2026): First qLDPC hardware demonstration on a superconducting platform. Custom Kunlun chip with 32 qubits and air-bridge long-range couplers for one specific BB code. Logical error rates ~9% per cycle. Not at breakeven.

Trapped ion — Quantinuum (multiple papers, 2024–2026): Demonstrated a [[25,4,3]] qLDPC code on the H2 processor in July 2024, achieving beyond-breakeven fidelity for a 4-logical-qubit GHZ state (99.5–99.7% after post-selection). The February 2026 Dasu et al. paper demonstrated computation with up to 94 logical qubits using iceberg error-detecting codes on the 98-qubit Helios system, though these used iceberg codes (a different code family) rather than the BB/GB qLDPC codes tested here.

Trapped ion — IonQ (this paper): Five distinct qLDPC codes, breakeven performance, 9× improvement over superconducting baseline. Forty ions, no transport.

Neutral atom (Atom Computing, Bluvstein et al.): Toric code demonstrations on reconfigurable atom arrays, but qLDPC-specific demonstrations are still primarily theoretical/simulation.

Surface code (Google Willow): Below-breakeven with exponential error suppression at distance 3→5→7 on superconducting qubits. Still the strongest absolute demonstration of error correction, but using the qubit-expensive surface code.

IonQ’s result occupies a specific niche: the best-performing qLDPC experiment to date, with the added flexibility argument. It does not yet match the absolute performance of Google’s surface code result (no exponential suppression with distance) or the computational scale of Quantinuum’s Helios experiments (94 logical qubits). But it provides the first experimental evidence that high-rate qLDPC codes can reach breakeven on any platform, and it does so with a remarkable breadth of codes on a single device.

CRQC Implications

I’ll connect this to my CRQC Quantum Capability Framework through three capabilities:

B.1: Quantum Error Correction. This paper extends the experimental evidence base for qLDPC codes from a single superconducting demonstration to a trapped-ion demonstration with 4–9× better error rates. Reaching breakeven with a code encoding 4 logical qubits in 18 physical qubits (a 4.5:1 ratio) rather than the surface code’s ~17:1 ratio for distance-3 reinforces the case that future CRQCs will use qLDPC codes, not surface codes. Every architecture team publishing in 2025–2026 already assumes this, but they have been assuming it without experimental backing. Now they have some.

B.4: Qubit Connectivity & Routing. IonQ’s team ran multiple code families with different connectivity requirements on a single device. That is a concrete advantage of all-to-all connectivity for error correction. They also software-optimized qubit-to-ion mappings for each code’s specific gate requirements, reducing weighted gate infidelity by 30–50% without hardware changes. For CRQC resource estimates that assume a specific code family and connectivity, this suggests trapped-ion platforms have more headroom for code optimization than fixed-connectivity alternatives.

E.1: Engineering Scale & Manufacturability. This cuts both ways. The OMG architecture’s ability to eliminate dedicated coolant ions improves the ion-utilization efficiency, which helps the scaling math. But 40 ions in a stationary chain is a long way from the thousands required for a CRQC. Scaling this approach will require either much longer chains (with attendant mode management challenges), modular architectures with photonic interconnects, or a transition to QCCD-style transport — each of which introduces engineering challenges the current paper does not address.

This paper does not change my assessment of CRQC timelines. We are still looking at 7–15 years depending on modality, as I discussed in the CRQC Scorecard. But it does strengthen the case for qLDPC codes as the error correction strategy that a CRQC will use, and it gives IonQ’s Walking Cat architecture its first experimental anchor point. The Walking Cat was a blueprint; this paper is the first brick.

What Comes Next

The obvious next steps for IonQ: demonstrate exponential error suppression with increasing qLDPC code distance (their BB5 family at distances 3, 4, 5 should allow this, but the data doesn’t yet show it), reduce leakage rates to enable erasure conversion instead of post-selection, and scale beyond 40 ions. The beam search decoder (co-authored by the same Nicolas Delfosse) was published in December 2025 and has already been used in this experiment; the decoder pipeline from theory to experiment is tight.

For the broader field, this paper accelerates a trend I’ve been tracking: the convergence of theoretical architecture proposals and experimental validation for qLDPC codes. Six months ago, qLDPC codes had one experimental data point (Wang et al., superconducting, ~9% error rates). Today they have two, across two hardware platforms, with the newer result at breakeven. That is still early. But the trajectory favors the code family that every serious fault-tolerant architecture is now designed around.

None of this changes the urgency of PQC migration. As I keep saying, the reason to act is not Q-Day predictions — it is the regulatory and business deadlines that are already set. But for those tracking the engineering trajectory toward a CRQC, this paper adds a concrete data point to a trend that has been mostly theoretical: the codes that would make a qubit-efficient CRQC possible are starting to work in hardware.