Table of Contents
I have been a skeptic of D-Wave’s claims for a long time. The company spent years marketing quantum annealing with a promotional intensity that often ran ahead of what the hardware could demonstrably do. When D-Wave announced the $550 million Quantum Circuits acquisition in January 2026, I treated it with caution: buying a prestigious Yale spinout does not automatically make you a competitive gate-based quantum computing company.
This Nature paper is the first result that moved my assessment. Not because of the press release framing (which oversells, as usual) but because of what the data actually shows.
August 5, 2026 — D-Wave Quantum has published a paper in Nature demonstrating a two-qubit entangling gate for dual-rail cavity qubits, the superconducting erasure qubit architecture it acquired through its $550 million purchase of Quantum Circuits Inc. in January 2026. The paper, titled “An entangling gate for dual-rail erasure qubits,” is the first peer-reviewed gate-model result published under the D-Wave banner. The research itself predates the acquisition: its preprint appeared in March 2025, and Nature received the manuscript in May 2025. This is therefore a major result from the acquired Quantum Circuits program, now published under D-Wave affiliation.
The bottom line: D-Wave’s controlled-Z (CZ) gate has a total error rate roughly five times higher than the best conventional two-qubit gates, yet surface code simulations using the gate’s measured error profile project error correction performance roughly double that of state-of-the-art depolarizing-noise gates. The structure of the errors, not their total magnitude, determines how well they can be corrected.
The paper reports a CZ gate completed in approximately 500 nanoseconds with an erasure rate of about 0.5% per gate, residual Pauli errors (after erasure detection) below 0.1%, and bit-flip errors suppressed to the 10⁻⁶ level. The gate preserves the error hierarchy that makes dual-rail cavity qubits attractive for quantum error correction: erasures (detectable errors) dominate over dephasing errors, which in turn dominate over bit-flips by orders of magnitude.
Gate performance in detail
The team, led by Nitish Mehta, James D. Teoh, and Taewan Noh with Robert Schoelkopf as senior author, used a so-called “Swap-Wait-Swap” (SWS) gate architecture. The gate temporarily moves a photon from one cavity to a transmon coupler, allows a dispersive interaction to entangle the two dual-rail qubits, and then returns the photon. Because the total number of excitations is preserved throughout the operation, any photon loss results in a detectable leakage event rather than a hidden error.
For a single CZ gate, the team measured an end-to-end circuit state fidelity of 99.60(1)% and a state purity of 99.46(3)%, which includes errors from state preparation, measurement, and single-qubit gates aggregated with the CZ gate itself. From repeated gate sequences (up to 103 gates), they extracted a conservative post-selected Pauli error bound of 0.12(1)% per CZ gate and a total erasure probability of 0.53(2)% per gate. Interleaved randomized benchmarking yielded a consistent estimate of 0.108(5)% error per CZ gate.
The error structure shows a clear asymmetry between the “control” and “target” qubits. Control qubit erasure rates (0.400% per gate) are roughly four times higher than target qubit erasure rates (0.096%), consistent with the lower coherence time of the coupler that the control qubit temporarily occupies during the gate. Dephasing follows a similar 3.5:1 ratio.
Surface code simulations
Using the Stim simulator, the team compared two noise models applied to surface code memory: their experimentally measured SWS gate error profile, and a standard two-qubit depolarizing noise channel at 0.1% error rate (representing state-of-the-art performance in conventional superconducting qubits).
The SWS gate error model produced Λ ≈ 27, where Λ is the factor by which the logical error rate decreases when the surface code distance increases by two. The depolarizing noise model at 0.1% produced Λ ≈ 14. Google’s Willow processor, the first system to demonstrate below-threshold surface code operation experimentally, measured Λ = 2.14 ± 0.02 in 2024.
A critical caveat: D-Wave’s Λ ≈ 27 comes from simulation with idealized assumptions (only CZ gate errors, perfect erasure checks, no single-qubit gate or measurement errors). Google’s Λ = 2.14 was measured on a real 105-qubit processor running an actual surface code. The paper acknowledges these models are “simplistic” and says that “more realistic simulations must include errors in the single-qubit gates, all measurements (including erasure checks) and idling errors, which reduce the value of Λ.”
The simulations also showed that D-Wave’s gate architecture allows erasure checks to be delayed to the end of each syndrome extraction round (rather than after every two-qubit gate) without losing the favorable scaling of erasure-based error correction. This “leakage skips subsequent gates” property, confirmed experimentally in the paper, could simplify the engineering of surface code circuits for erasure qubits.
Context and concurrent work
The paper emerges seven months after D-Wave completed its acquisition of Quantum Circuits, the Yale spinout co-founded by Rob Schoelkopf. Schoelkopf, who co-invented the transmon qubit that underpins Google’s, IBM’s, and most other superconducting quantum computers, is now D-Wave’s chief scientist. In June 2026, D-Wave unveiled a gate-model roadmap targeting 100 logical qubits by 2032, with the dual-rail architecture as its foundation.
The D-Wave press release accompanying the paper states that the company’s roadmap targets a Lambda of 10, which is well below the Λ ≈ 27 from the simplified simulation. D-Wave chief scientist Schoelkopf said the entangling gate “is already integrated into our gate-model systems, where it is delivering comparable performance.”
The paper also notes concurrent work from a Chinese group at the International Quantum Academy in Shenzhen. Huang et al., published in Nature Physics earlier in 2026, demonstrated logical multi-qubit entanglement using a different implementation of dual-rail erasure qubits based on pairs of tunable transmons rather than microwave cavities.
My Analysis
The counterintuitive result, examined
The headline number from this paper is the Λ comparison: D-Wave’s gate, with roughly 0.5% total error, outperforms a 0.1% depolarizing-noise gate in surface code simulations by a factor of two (Λ ≈ 27 vs. Λ ≈ 14). That inversion is genuine and it is grounded in well-established theory about erasure channels, not in speculative modeling.
The physics is straightforward. When a quantum error is detectable (an erasure), the error correction code knows where it occurred and can correct for twice as many such errors compared to Pauli errors at the same code distance. The surface code threshold for pure erasure noise is approximately 25%, compared to roughly 1% for depolarizing noise. So a system that converts most of its errors into detectable erasures gets to operate much further below its own threshold, which translates to faster error suppression as you scale the code.
Where I part company with the press release framing is in treating this simulated Λ as a direct comparison to experimental results from other platforms. The paper’s Λ ≈ 27 is a simulation using only CZ gate errors with perfect erasure checks and no measurement noise. Plug in realistic single-qubit gate errors, imperfect erasure detection, measurement errors, and idling noise, and that number will drop. The paper itself says as much. Schoelkopf’s team is honest about this limitation, and their roadmap target of Λ = 10 (not 27) reflects that honesty.
Google’s Λ = 2.14 was extracted from a physical experiment with all of those real-world imperfections included. That number may improve as Google’s hardware improves. The comparison that matters is not D-Wave’s simulation against Google’s experiment; it is what happens when D-Wave builds an actual surface code on actual hardware and measures Λ under real conditions. The paper does not do that, and the promised companion publication is described as covering simulations and methodology, not necessarily hardware QEC.
Until then, I read this result as strong evidence that the gate concept works as intended and that the noise properties required for erasure-based QEC are preserved, not as proof that D-Wave has leapfrogged the field in error correction.
What the gate actually proves
Strip away the simulation projections and evaluate the experimental results on their own terms. Three things stand out.
First, the error hierarchy is preserved during the two-qubit gate. This was the open question for dual-rail cavity qubits: previous work from the Schoelkopf group had demonstrated high-fidelity single-qubit gates and erasure detection, but nobody had shown that a two-qubit entangling operation could maintain the favorable noise structure. Erasure rates dominate Pauli errors by roughly 5:1. Dephasing dominates bit-flips by roughly three orders of magnitude (10⁻³ vs. 10⁻⁶). Both hierarchies survive the gate. For anyone tracking the CRQC Quantum Capability Framework, this is progress on capability B.1 (Quantum Error Correction): a prerequisite for surface code implementations using erasure qubits has been experimentally satisfied.
Second, the leakage propagation behavior is unusually well structured. In most superconducting qubit architectures, leakage (a qubit leaving the computational subspace) is one of the most damaging error types because it can spread correlated errors across the system. In the SWS gate, if a qubit has already leaked to the vacuum state before the gate, the CZ interaction does not activate. Subsequent gates involving that qubit are skipped. If photon loss occurs during the gate itself, the partner qubit can acquire conditional dephasing (a controlled phase of unknown angle), but this propagation is bounded and well characterized. The paper demonstrates these properties both theoretically and experimentally (Fig. 4), and the bounded propagation has a practical consequence: erasure checks can be batched at the end of a syndrome extraction round instead of being performed after every gate. Fewer mid-circuit measurements means simpler circuits and fewer opportunities for measurement-induced errors.
Third, bit-flip suppression to the 10⁻⁶ level is remarkable by any standard. The paper reports total bit-flip probability bounded at a few parts per million per CZ gate, and the authors suspect even this tiny rate is dominated by photon loss events being misidentified as codespace events rather than genuine bit-flips. For error correction codes designed to exploit biased noise (such as tailored XZZX surface codes or thin rectangular codes), this extreme bias opens additional optimization pathways. Whether those pathways yield practical gains at scale remains an open research question, but the measured bit-flip rate is exceptionally low for a superconducting gate, though cross-platform comparisons require matched definitions and post-selection policies.
What the paper does not prove
A few things that are absent and worth being explicit about.
No surface-code logical qubit or hardware QEC experiment is reported. (A dual-rail qubit is itself an encoded qubit, but the outer error-correcting code that would demonstrate scaling with code distance is absent.) The QEC performance is entirely simulated. This paper reports no hardware surface code, no experimental below-threshold operation, and no measured error suppression with increasing code distance. The companion paper (J.D.T., manuscript in preparation), described in the text as a fuller treatment of surface-code simulations and methodology, may provide more realistic Λ estimates with additional noise sources. Whether it will include experimental logical qubit data is not stated.
The simulation uses a simplified noise model. Only CZ gate errors are included. Single-qubit gate errors, measurement errors, erasure check errors, and idling errors are all absent. The paper states this clearly and repeatedly. When those are added, Λ will decrease. The question is by how much.
The unexplained nonlinear degradation at higher gate depths is a flag. When the team repeated the CZ gate more than about 15 times, both fidelity and purity degraded faster than the linear model predicts, following an approximately quadratic curve. The authors attribute this to drift in calibration parameters or fluctuations in the coupler transmon frequency, and note that dynamical decoupling does not fix it. This kind of systematic drift, if not resolved, could limit circuit depth in practice and would show up as a performance ceiling in real QEC experiments.
The paper does report approximately 0.02% post-selected SPAM error for its end-of-the-line erasure-detected measurements. What it does not establish is the performance of imperfect erasure checks inside a scaled QEC circuit. The surface-code simulations assume perfect erasure checks, and the consequences of realistic check errors, measurement latency, and multi-qubit scaling are deferred.
The Schoelkopf factor
I want to draw attention to something about the authorship that has strategic implications beyond the physics.
Rob Schoelkopf co-invented the transmon qubit in 2007. The transmon is the workhorse of superconducting quantum computing. Google’s Sycamore and Willow processors, IBM’s Eagle and Heron processors, Rigetti’s Ankaa-class processors, and processors from IQM, OQC, and QuantWare all use transmons or direct descendants. When the person who invented the dominant qubit modality publishes a paper arguing that his newer invention (dual-rail cavity qubits, developed at Yale starting around 2020) offers a better path to fault tolerance, that carries technical weight independent of whatever company name is on the letterhead.
It also carries weight that D-Wave paid $550 million for this ($300 million in stock, $250 million in cash). That is not a research grant; it is a commercial bet on the dual-rail architecture being the foundation of a product roadmap. The Nature paper is a marquee scientific asset that arrived with the acquisition rather than a result generated after the two organizations combined, but the numbers are credible, and the research program now operates inside D-Wave’s engineering organization.
(The author list tells its own story: present addresses include Q-CTRL, NVIDIA, Atom Computing, Microsoft Quantum, IBM Quantum, Rigetti, and Alice & Bob. Schoelkopf’s Yale lab has been one of the most prolific talent pipelines in superconducting quantum computing for two decades. Some of the people who built this gate are now at the companies D-Wave intends to compete with.)
Where this sits in the CRQC picture
For readers tracking the path to a cryptographically relevant quantum computer, this paper is relevant but does not change the timeline.
The erasure qubit approach could reduce the code distance, and therefore the number of encoded qubit units, required to reach a given logical error rate. D-Wave has claimed up to a 10× reduction in physical-qubit overhead compared to conventional transmons, but this paper does not establish that number for a full fault-tolerant system. A meaningful comparison would need to account for the hardware each dual-rail qubit requires (two cavity modes, couplers, ancilla transmons, readout resonators) and the full QEC stack including decoder requirements and magic-state overhead. Until such a matched resource estimate exists, the implications for CRQC resource estimates and Q-Day timelines remain speculative.
D-Wave’s roadmap calls for 17 physical qubits in 2026, 49 in 2027, 181 in 2028, 10 logical qubits by 2030, and 100 logical qubits by 2032. As I analyzed when the roadmap was announced, D-Wave is entering the scaling race with a credible two-qubit gate primitive but without a published multi-qubit integrated processor or hardware surface-code result comparable to Google’s Willow, IBM’s Heron, or Quantinuum’s Helios. The technical premise is sound, but the integration gap is real.
This paper does not close that gap. It validates one of the foundational claims (the two-qubit gate preserves the error hierarchy) and provides simulation evidence that the architectural advantages translate to better QEC performance. That is necessary but not sufficient. The milestones that will actually matter for the CRQC timeline are: demonstrating a logical qubit with below-threshold performance on real dual-rail hardware (capability B.3), and showing that Λ holds up when measured experimentally rather than simulated. Neither has happened yet.
Who else is betting on structured noise
D-Wave is not the only team pursuing qubits with built-in error structure. This paper exists within a broader shift in the field away from treating all errors as equivalent and toward engineering qubits where the dominant errors are the cheapest to correct.
AWS published its Ocelot chip results in Nature in February 2025. The Ocelot chip uses concatenated cat qubits, which suppress bit-flips through engineered two-photon dissipation. The resulting noise bias can be exploited by repetition codes. Alice & Bob, the French startup pursuing the same approach, has reported preliminary hour-scale idle bit-flip stability (33–60 minutes at 95% confidence in its September 2025 Galvanic Cat results, before testing under a two-qubit gate). The cat qubit approach uses a different noise bias (bit-flip suppression through dissipation engineering) but pursues the same strategic insight: structured noise reduces QEC overhead.
The Huang et al. paper from Shenzhen’s International Quantum Academy, published in Nature Physics earlier this year, integrated four dual-rail erasure qubits using tunable transmons rather than cavities and demonstrated multi-qubit entanglement across the three that were operational. Their logical single-qubit gate error rates reached the 10⁻⁵ level with post-selection. The transmon-based approach may offer different scaling tradeoffs than D-Wave’s cavity approach, though direct comparison requires matched benchmarks that do not yet exist.
Google and USTC continue to push conventional transmon surface codes, with Google’s Willow providing the most relevant experimental surface-code reference point for comparison. The question is whether the conventional transmon surface-code approach (lower physical error rates on standard qubits) or the structured-noise approach (higher total error rates but more correctable errors) will reach practical fault tolerance first.
I do not have a strong prior on which approach wins. Both have credible theoretical backing and both face serious engineering challenges at scale. What I can say is that this D-Wave paper strengthens the case for the structured-noise approach with real experimental data, and the field would benefit from a matched head-to-head comparison using the same code family, distance convention, and decoding methodology on different qubit types.
What to watch next
Three milestones will determine whether this paper is a footnote or a turning point in D-Wave’s gate-model program.
The companion QEC paper (J.D.T., manuscript in preparation) is described as a fuller treatment of surface-code simulations. Whether it will also report experimental logical qubit data is not stated. Either way, the key question is what Λ looks like once realistic noise sources (imperfect erasure checks, measurement errors, single-qubit gate errors, idling noise) are included in the model. D-Wave’s roadmap targets Λ = 10; whether the structured-noise advantage survives a realistic full-stack analysis will determine how aggressively the roadmap can be credited.
The 17-qubit roadmap system is the first test of whether D-Wave can turn this gate primitive into a larger integrated QEC platform. Scaling from two qubits to seventeen introduces fabrication yield, calibration complexity, and crosstalk challenges that this two-qubit paper does not address. There is also an open question about implementation: the Nature experiment uses 3D microwave cavities, while some D-Wave investor materials have described planned systems as “dual-rail transmon-based.” How the cavity-based device demonstrated here maps onto roadmap systems is itself something to watch.
The resolution of the unexplained nonlinear degradation at higher gate depths is worth tracking. The authors report approximately quadratic fidelity loss beyond about 15 repeated gates and candidly state they do not understand the root cause. If this turns out to be a fundamental limitation of the coupler design rather than a calibration drift issue, it would represent a deep-circuit stability risk that could limit practical QEC performance. (The Supplementary Information reports repeated IRB benchmarking across seven two-qubit systems, which provides some evidence of consistency, but does not resolve the degradation mechanism.)
For now, the honest read is this: D-Wave has published a technically sound Nature paper that validates key architectural assumptions about dual-rail erasure qubits. The numbers are good. The error hierarchy is real. The QEC projections, if confirmed experimentally, would represent a genuine advance in the efficiency of fault-tolerant quantum computing. The gap between “if confirmed” and “confirmed” is where the story gets interesting.
