Quantum Computing Paradigms: Silicon-Based Qubits

(For other quantum computing paradigms and architectures, see Taxonomy of Quantum Computing: Paradigms & Architectures)

What It Is

Silicon-based quantum computing refers to qubits implemented using silicon semiconductor technology, leveraging the existing CMOS fabrication infrastructure. The most common silicon qubit implementations are spin qubits – using the spin of an electron or the spin of an atomic nucleus embedded in silicon as a qubit. Two prominent examples are: (1) Quantum dot spin qubits – single electrons confined in transistor-like silicon quantum dot structures, where the electron’s spin-up vs spin-down (relative to a magnetic field) represents |0⟩ vs |1⟩; (2) Donor spin qubits – using dopant atoms (like a phosphorus atom substituting a silicon atom in the lattice) whose extra electron (or nuclear spin) serves as a qubit. Silicon is attractive because it’s the foundation of the microelectronics industry – billions of nanoscale transistors are made with ultra-high precision on silicon wafers, so if qubits can be made in silicon, one could in principle scale using similar processes. Moreover, isotopically purified silicon (Si-28) is a very clean environment with zero nuclear spins (since Si-28 has none), leading to extremely long spin coherence times for electron and nuclear spins (since they’re not disturbed by fluctuating nuclear spin noise)​. This approach is sometimes called “silicon quantum dot computing” or “silicon spintronics for quantum”.

Key Academic Papers

A foundational proposal was by Bruce Kane (1998): “A silicon-based nuclear spin quantum computer.” Kane’s paper outlined how donor atoms (like phosphorus) in silicon could be used to realize qubits (nuclear spins of P donors) and coupled via the electrostatic interaction modulated by gate electrodes. This sparked the silicon quantum computing field. It suggested using the well-developed silicon nanofabrication to precisely place donor atoms and control them. In the early 2000s, researchers like Lieven Vandersypen, Daniel Loss, and others also worked on electron spin qubits in quantum dots (Loss & DiVincenzo had a famous 1998 paper about spin qubits in III-V quantum dots, which later was applied to silicon)​. The first experimental breakthrough in silicon spin qubits came in 2012, when two separate groups (One led by Andreas Morello at UNSW, Australia, and another by Michelle Simmons’s team) demonstrated single-shot readout and control of a single phosphorus donor electron spin in silicon (Morello’s team achieved >99% fidelity readout and a long coherence time using isotopically enriched silicon).

Around the same time, Petta and others had shown coherent control of two-electron spin qubits in GaAs double dots (2005), and by mid-2010s, efforts shifted to silicon MOS or Si/SiGe quantum dots to leverage longer coherence. In 2015, the first two-qubit gate in silicon (a controlled rotation between two electron spins in a double quantum dot) was demonstrated by Vandersypen’s group (Veldhorst et al., Nature 2015) with about 90% fidelity. That was key academic progress proving silicon spins can be entangled. Since then, many improvements: e.g., in 2019, a two-qubit gate fidelity around 98% was shown (X. Xue et al.), and in 2022, as referenced by a QuTech paper, a six-qubit quantum processor in silicon was operated with high single- and two-qubit fidelity. So the academic timeline progressed from single donor spin qubit control (2012) to two-qubit logic (2015) to multi-qubit (2021-2022).

How It Works

Silicon spin qubits can take a few forms:

Quantum Dot Spins

Typically, nanofabricated electrostatic gates on a silicon substrate (often an interface of Si/SiO2 or a Si/SiGe heterostructure) create a potential well that confines an electron. By tuning gate voltages, one can isolate a single electron in a tiny quantum dot (~tens of nanometers). That electron has a spin-1/2. Under an external static magnetic field (e.g., B ~ 1 Tesla), the spin-up and spin-down split in energy by the Zeeman effect (e.g., around 20-30 GHz difference typically). These two levels form the qubit |0⟩ and |1⟩. Single-qubit rotations are done by applying a resonant microwave magnetic field (electron spin resonance, ESR) or, more practically in these devices, by electric fields exploiting spin-orbit or micromagnets to induce spin rotations (EDSR – electric dipole spin resonance). Two-qubit gates are generally implemented via the exchange interaction: if two quantum dots are brought close (or a barrier between them lowered), the electrons’ wavefunctions overlap and their spins interact (Heisenberg exchange coupling). By turning on exchange coupling between two spins for a precise duration, one can implement a CNOT or CZ (exchange acts like a two-qubit interaction $H_{ex} = J \mathbf{S_1}\cdot\mathbf{S_2}$ which can generate entanglement). Another method is via capacitive coupling: if each spin’s energy depends slightly on charge position, two nearby dots can have a spin-state-dependent charge distribution, yielding an effective two-spin coupling without direct tunneling.

The quantum dot approach is very analogous to a transistor: in fact, a recent 6-qubit device essentially looks like a linear array of 6 quantum dots controlled by gate electrodes just like 6 tiny transistors in a row​. The device is operated in a dilution fridge at ~50 mK. It requires careful tuning of many gate voltages to isolate exactly one electron per dot and set the desired tunnel coupling between neighboring dots. These devices are sometimes called silicon MOS quantum dots (if using metal-oxide-semiconductor structure) or Si/SiGe quantum dots (if using a quantum well of Si in a SiGe matrix).

Donor Spins

Here, one uses e.g. P donors in Si. A phosphorus atom (with one more proton than silicon) has one extra electron loosely bound (like a hydrogen atom in silicon). At cryogenic temperatures, that electron is bound to the donor unless excited. The electron spin or the phosphorus nuclear spin can be used as qubit. Donors can be placed by ion implantation or STM lithography (Simmons’ group can place single P atoms with atomic precision using scanning tunneling microscope and hydrogen-resist lithography). Single-qubit control is by ESR (for electron) or NMR (for nucleus) with microwave fields. Two-qubit gates between donors are harder if they’re far apart – originally Kane proposed using the electrostatic interaction modulated by surface gates to couple nuclear spins (via electron intermediaries). Some experiments have coupled two donor electrons via exchange by bringing them close (couple donors ~10-20 nm apart, control their overlap). But donor approaches are less advanced in two-qubit gates compared to quantum dots because positioning and controlling exchange between donors is challenging.

Hole spin qubits

A recent variation is using the spin of a hole (missing electron) in silicon or germanium quantum dots. Holes have strong spin-orbit coupling, which means they can be manipulated purely electrically (no need for an on-chip microwave line; a fast voltage pulse can rotate a hole spin due to spin-orbit coupling). Several groups (e.g., in France, Australia) are exploring hole qubits, especially in silicon quantum wells and germanium quantum wells, with some success in single-qubit control and even two-qubit coupling in Ge.

Topological in Silicon?

There’s also work on proximitizing silicon with superconductors to perhaps host Majorana modes (though more common in InSb nanowires, not mainstream silicon; we’ll cover topological separately).

Comparison To Other Paradigms

Silicon spin qubits are solid-state like superconductors, but operate with completely different physics (spin vs circuit) and at higher frequency (typically microwave ESR at ~10-50 GHz). A big promise of silicon is leveraging the manufacturing scale and expertise of the semiconductor industry – billions of classical transistors on a chip vs just a handful of qubits in other approaches. In principle, once one can reliably fabricate and operate a single silicon qubit, making thousands on a chip is just a matter of reticle size and fabrication, not fundamentally limited by physics. Indeed, companies like Intel have been adapting their fabrication to quantum dot devices (they made a 48-dot array test chip on 300mm wafers). The ability to use CMOS processes also means integration of classical control electronics on the same chip or in the same stack (imagine cryo-CMOS control circuits adjacent to qubits to reduce wiring).

In terms of performance, silicon spin qubits have very long coherence when isolated – single electron spins in purified silicon can have $T_2^*$ (dephasing time) of order microseconds and $T_2$ (echo) of up to milliseconds, and single nuclear spins can have coherence times up to seconds (even minutes for certain isotopes)​. These times are shorter than trapped ions (which can be seconds) but much longer than superconducting (microseconds). However, when doing operations, they need to be tuned precisely; and fabrication disorder can cause variability in qubit frequencies and interactions.

Gate speeds: single-spin rotations are quite fast (~ns to perform a $\pi$ rotation with typical ESR Rabi frequencies of tens of MHz if power allows). Two-qubit exchange gates can also be fast (~tens of ns). In experiments, gate times are on the order of tens of nanoseconds to a few microseconds depending on qubit spacing and approach – so roughly similar or a bit slower than superconducting gates, but much faster than atomic gates. So, they have a fast gate advantage like superconductors, and a long coherence advantage approaching that of atomic qubits (if environment is clean).

The major challenge and difference is scalability in practice: Each silicon quantum dot qubit currently needs careful tuning of multiple voltage gates (Coulomb blockade, etc.), and variability in threshold voltages means each dot might behave differently. This is reminiscent of early transistor development where each transistor had to be tuned – but eventually, CMOS made them uniform. There’s hope similarly for qubits, but it’s non-trivial because qubits need analog precision whereas digital transistors just need on/off.

Compared to superconducting qubits, silicon spin qubits are smaller in physical size (a quantum dot ~50 nm across vs a transmon ~100-200 micrometer resonator region), which means higher density. They also don’t inherently require extreme wiring – though you do need DC gate voltages and some microwave lines, but one could multiplex controls or use word lines / bit lines like in a memory array to address many qubits with fewer lines. The cooling requirement is similar (they also need dilution fridge, often even colder ~50 mK to reduce electron temperature for stable spin initialization). Another difference: readout of spin qubits is often slower and more complex than measuring a superconducting qubit. Typically, spin readout is done via a spin-to-charge conversion (e.g., using a quantum dot next to the qubit dot as a charge sensor – when spin is up, an electron can tunnel and change a charge sensor current, etc.) and this can take tens of microseconds to milliseconds to integrate a signal with low noise electronics​. Superconducting qubits can be read out in microseconds via microwave resonator. However, improvements like charge sensing with rf reflectometry (rf-QPC or rf-SET) can speed up spin readout to maybe a few microseconds.

Compared to trapped ions or atoms, silicon qubits have much shorter coherence, but they are electrical devices so they can be engineered on-chip and potentially integrated with classical electronics. The vision is a quantum chip that is manipulated similarly to how a classical chip is – which is appealing for eventual integration into existing tech. Also, no vacuum or giant optical setups – just a cryostat and electronics, which is already the domain of quantum computing setups.

One more comparison: NV centers in diamond are another solid-state spin qubit (not silicon but carbon lattice with a nitrogen impurity). NV centers have very long coherence at room temperature, but controlling and scaling them is difficult. Silicon spin qubits at low temperature might offer better scalability with chips, albeit needing cryogenics.

Current development status:

• Academic groups have realized up to 6 qubits in one device (QuTech’s 6 spin array with 2-qubit gates between neighbors, 2022)​. That particular device achieved average single-qubit gate fidelities ~99.8% and two-qubit fidelities ~99.0% (between certain pairs) – a significant achievement demonstrating the viability of a small silicon quantum processor​. They even ran a few quantum algorithms like a simplified version of Grover’s search on 2 qubits, and implemented a rudimentary quantum error correction code (3-qubit bit-flip code).
• Intel has been investing in silicon qubits (their approach uses a 300mm fab in Oregon to make devices on silicon wafers). In 2018 they showed a 49-electron quantum dot array “Chip (code-named Tangle Lake)” but that was mostly a test vehicle; they have since focused on improved qubits with better yield. In 2020 they reported successful fabrication of arrays and in 2022, Intel announced a chip called “Horse Ridge” (a cryogenic control chip) and progress on two-qubit gates. They made a quantum dot spin qubit chip with integrated cryo-CMOS control on the same die (which is a step toward scaling by embedding control electronics at low temp).
• Silicon Quantum Computing (SQC): An Australian startup (from UNSW team of Simmons) focusing on donor-based qubits. They achieved 3-qubit entanglement (with 1 nucleus and 2 electron spins on 2 P donors) in 2021 and implemented a small logic algorithm. They aim at donor-based processors but that’s a challenging but potentially rewarding route.
• HRL Laboratories (USA, jointly owned by Boeing and GM) has a program on silicon spin qubits. In 2022, HRL demonstrated a 3-qubit silicon device that achieved quantum error correction of a logical qubit (a 3-qubit code correcting single bit-flip error) with logical fidelity exceeding physical – one of the first error correction demonstrations in any solid-state platform. They had 3 physical qubits with two-qubit gates to create a logical qubit and did repetitive error correction cycles.
• Quantum Motion (UK) and Rigetti (who acquired a spin qubit company) and others are in this space too.
• On the technology side, many fundamental improvements: e.g., use of isotopically pure Silicon-28 wafers (natural Si has 4.7% Si-29 with nuclear spin which can decohere electrons; using enriched Si-28 drastically improved coherence). Also, multi-gate structures for tunable coupling (like barrier gates to control exchange precisely).

In summary, silicon spin qubits are at the few-qubit demonstration phase – around 1 to 6 qubits have been coherently controlled in labs with high fidelity, but they have not yet reached the tens or hundreds of qubits integrated with control that superconducting or neutral atom approaches have. It’s an active race to go from these linear 2-6 qubit devices to 10-50 qubit devices in next years, and to solve packaging and control integration for larger arrays.

Advantages

• CMOS compatibility and scalability: The biggest selling point – one can leverage the mature semiconductor fab industry. The inference is that scaling from 6 to many is an engineering task, not a fundamental showstopper. Companies like TSMC, Intel could potentially mass-produce quantum chips if the designs are solid. This could lead to rapid scaling once we hit a threshold of viability, akin to how classical integrated circuits scaled.
• Long coherence and possible operation at higher temperature: Spins in silicon can maintain coherence extremely well especially if nuclear spins are eliminated or controlled. Also, there’s some evidence electron spins might function even up to a few Kelvin if design is optimized, which could allow simpler cryogenics (some prototypes operate at 1.1 Kelvin with spin qubits, albeit with reduced coherence). There’s research on donor nuclear spin qubits that hold quantum info for hours (but then you need an interface to use them in circuits).
• Compact size and potential for integration: Because qubits are so small, one could imagine integrating millions of qubits per square millimeter if technology allowed. Also, integration with classical electronics is possible on the same chip or same package (imagine memory cell arrays where each cell is a qubit, and classical logic on periphery for read/write, similar to DRAM architecture). This synergy is powerful: classical controllers can be placed adjacent to minimize latency and wiring complexity (for instance, multiplexers and DACs at cryo that address many qubits, etc.).
• Advances in multi-qubit operations: The demonstration of a six-qubit device with solid fidelity suggests these qubits can perform non-trivial circuits. With error rates around 1% for 2-qubit gates and <0.2% for 1-qubit, they are at the threshold of NISQ-era algorithms and maybe small error-correcting codes. So they have caught up in fidelity to other platforms (though still slightly behind the best superconducting or ion gate fidelities, which are >99%).
• Relative stability once calibrated: A subtle advantage: if kept at stable cryo conditions, a silicon chip could in principle run a long time. There’s no lasers or atomic reloading, etc. Many challenges but not the same as capturing atoms – the qubits are fixed in a solid matrix. If variability and drift can be managed (via calibration or feedback), it could run many cycles autonomously. Also, since it’s a solid, it might be easier to protect from environmental noise by shielding, etc.

Disadvantages

• Extreme fabrication precision needed: While it’s in silicon, the tolerance for disorder is very low. Tiny variations in gate voltage or dot size can change qubit resonance frequencies or exchange coupling by a lot. The six-qubit result indicated “to achieve high precision as for single qubits in larger arrays, careful engineering was needed.” In large arrays, ensuring uniformity to keep qubits addressable without each one being individually tuned is a challenge. There are strategies like tuning each qubit frequency via local gate bias (like how each transmon has a flux tuner, each spin qubit might require a local adjust). Still, variability has been a big issue historically – many devices have qubits that behave differently or some that fail to calibrate.
• Two-qubit coupling range: Typically, exchange coupling is short-range – usually only between nearest neighbor dots (~tens of nm). Achieving interactions beyond nearest neighbor requires either moving electrons (there are ideas of shuttling spins through quantum dot arrays like a shift register) or coupling via an intermediate like a superconducting resonator (some hybrid experiments embed a quantum dot in a resonator to mediate long-range coupling). Without that, connectivity is basically a 1D line or 2D grid of nearest neighbors, which may require many swap operations for distant qubit interactions.
• Control electronics challenges: While integration is possible, currently each qubit needs a few voltage controls (for dot confinement and tunnel coupling) plus at least one microwave control for spin rotation (which could be a global ESR line rather than per qubit). For small qubit counts, these are managed with external instruments (AWGs, etc.), but for hundreds or thousands, one must integrate control. Cryogenic CMOS controllers exist (like Intel’s Horse Ridge chip can output multiple microwave tones at mK, and Zurich Instruments / EPFL had a Cryo SoC for spin control), but putting all that and connecting it to potentially millions of gates on chip is a formidable engineering problem. So wiring and control complexity, though maybe easier than superconductors because lower frequency and DC lines mostly, is still significant.
• Temperature constraints: These qubits need to be at ~millikelvin for best performance (some talk of operation at 1-4 K for quantum dots with engineered spin-orbit, but fidelity suffers). That means dilution refrigerators, which for large qubit counts will have to handle more heat from control lines. However, since much can be DC or low freq, the heat load might be more manageable than thousands of microwave lines needed for superconductors.
• Readout is slow-ish and not yet multiplexed widely: If readout takes ~100 μs per qubit, and if done sequentially, that could be slow for large number (though one can read many spins in parallel by having many charge sensors or a sensor per qubit or frequency multiplexing the readout). Research is ongoing to do rf reflectometry with multiplexing so many dot sensors share a line at different frequencies.
• Comparatively behind in qubit count: Only up to 6 qubits shown vs >50 in others. There’s a lot of catch-up. But one hopes scaling in silicon can accelerate.

Impact On Cybersecurity

If silicon qubits can be scaled massively using industry processes, they could lead to very large quantum computers once error correction is manageable. One can imagine a future where a quantum chip with, say, 1 million physical spin qubits (maybe on multiple tiles connected by bonding) provides 1000 logical qubits after error correction. Such a device absolutely could break current cryptography – running Shor’s algorithm on 2048-bit RSA might need a few thousand logical qubits and billions of gate operations (which might be borderline but could be feasible if each gate is ~ns and you have error correction to handle long circuits). The timeline is uncertain: currently, 6 qubits is far from that. But if in ten years they reach e.g. 1000 physical spin qubits with good fidelity, it may rival superconducting approaches.

One advantage from a cryptographic standpoint is that if quantum computing moves into silicon fabs, it might accelerate the availability of large devices (especially if classical computing giants like Intel, Samsung, or TSMC fully devote fabs to it). This could shorten the time to a cryptographically relevant quantum computer once the basic unit (qubit) performance is proven.

So, while silicon qubits might be a bit behind now, they could catch up and become the technology that delivers large-scale quantum computers. The existence of this path reinforces the need to transition to quantum-safe cryptography before such machines exist. Particularly since a quantum computer in silicon could potentially be integrated with existing computing infrastructure (imagine a quantum accelerator chip in a server rack, not just big specialized labs), making it more accessible.

Future Outlook

The next steps for silicon qubits will be demonstrating 2D arrays (so far 6 qubits was a linear array; a 2×2 or 3×3 array would add complexity of crosstalk management, but some groups are working on 2D dot arrays), improving multi-qubit calibration automation, and integrating cryo-electronics. We may see a 10-20 qubit device by mid 2020s if all goes well, and perhaps 50-100 qubits in a more integrated fashion by end of 2020s. There’s also interest in using quantum dot spin qubits for NISQ applications if they can get to maybe 8-16 qubits with decent fidelity – they might attempt small quantum chemistry simulations or optimization (though likely others will surpass them in qubit count by then). But error correction experiments will definitely be on the menu: demonstrating a logical qubit with spin qubits (beyond the 3-qubit bit flip code to maybe a 7-qubit Steane code or surface code on a small patch).

Another promising line is shuttling spin qubits: moving electrons across quantum dot arrays to ferry quantum info (like how ions move in ion traps). There was a recent result of shuttling an electron spin across 530 nm in 5 dots with 99.3% fidelity (Biquel et al. 2021) – which is like a conveyer belt for qubits. If one can shuttle, you can have long-range interaction by moving qubits adjacent temporarily. That could vastly improve connectivity in a larger array and support modular scaling (like move qubits to a region to interact then move back).

Also, fusion of donor and dot approaches might yield hybrid multi-qubit registers: donors as memory, dots as interface. And exploring hole qubits in Ge/Si as they can be operated faster (though coherence is a bit lower, but still sufficient).

If or when tech giants fully join (e.g., if Intel or IBM commit to scaling spin qubits as much as they have with superconductors), we could see rapid progress. IBM so far is more on superconductors, but not dismissing spins either; Intel is on spins; Google’s quantum arm hasn’t pursued silicon spins publicly, but who knows, they might if superconductors hit limits.

In conclusion, silicon-based qubits offer a path to merge quantum computing with the existing semiconductor ecosystem. They bring together the quantum world and Moore’s law culture. Should they succeed, they could produce the large, complex quantum processors needed to crack cryptography or solve classically intractable problems – but a lot of engineering and physics remains to be conquered first.